Dr Andrew Scott
G7VAV
Senior Lecturer
School of Computing
and Communications
D35 InfoLab21
Lancaster University
Lancaster, LA1 4WA
United Kingdom
School of Computing
and Communications
D35 InfoLab21
Lancaster University
Lancaster, LA1 4WA
United Kingdom
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msr-index.h
001: #ifndef _ASM_X86_MSR_INDEX_H 002: #define _ASM_X86_MSR_INDEX_H 003: 004: /* CPU model specific register (MSR) numbers */ 005: 006: /* x86-64 specific MSRs */ 007: #define MSR_EFER 0xc0000080 /* extended feature register */ 008: #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 009: #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 010: #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 011: #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 012: #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 013: #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 014: #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 015: #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 016: 017: /* EFER bits: */ 018: #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 019: #define _EFER_LME 8 /* Long mode enable */ 020: #define _EFER_LMA 10 /* Long mode active (read-only) */ 021: #define _EFER_NX 11 /* No execute enable */ 022: #define _EFER_SVME 12 /* Enable virtualization */ 023: #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 024: #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 025: 026: #define EFER_SCE (1<<_EFER_SCE) 027: #define EFER_LME (1<<_EFER_LME) 028: #define EFER_LMA (1<<_EFER_LMA) 029: #define EFER_NX (1<<_EFER_NX) 030: #define EFER_SVME (1<<_EFER_SVME) 031: #define EFER_LMSLE (1<<_EFER_LMSLE) 032: #define EFER_FFXSR (1<<_EFER_FFXSR) 033: 034: /* Intel MSRs. Some also available on other CPUs */ 035: #define MSR_IA32_PERFCTR0 0x000000c1 036: #define MSR_IA32_PERFCTR1 0x000000c2 037: #define MSR_FSB_FREQ 0x000000cd 038: 039: #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 040: #define NHM_C3_AUTO_DEMOTE (1UL << 25) 041: #define NHM_C1_AUTO_DEMOTE (1UL << 26) 042: #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 043: 044: #define MSR_MTRRcap 0x000000fe 045: #define MSR_IA32_BBL_CR_CTL 0x00000119 046: #define MSR_IA32_BBL_CR_CTL3 0x0000011e 047: 048: #define MSR_IA32_SYSENTER_CS 0x00000174 049: #define MSR_IA32_SYSENTER_ESP 0x00000175 050: #define MSR_IA32_SYSENTER_EIP 0x00000176 051: 052: #define MSR_IA32_MCG_CAP 0x00000179 053: #define MSR_IA32_MCG_STATUS 0x0000017a 054: #define MSR_IA32_MCG_CTL 0x0000017b 055: 056: #define MSR_OFFCORE_RSP_0 0x000001a6 057: #define MSR_OFFCORE_RSP_1 0x000001a7 058: 059: #define MSR_IA32_PEBS_ENABLE 0x000003f1 060: #define MSR_IA32_DS_AREA 0x00000600 061: #define MSR_IA32_PERF_CAPABILITIES 0x00000345 062: 063: #define MSR_MTRRfix64K_00000 0x00000250 064: #define MSR_MTRRfix16K_80000 0x00000258 065: #define MSR_MTRRfix16K_A0000 0x00000259 066: #define MSR_MTRRfix4K_C0000 0x00000268 067: #define MSR_MTRRfix4K_C8000 0x00000269 068: #define MSR_MTRRfix4K_D0000 0x0000026a 069: #define MSR_MTRRfix4K_D8000 0x0000026b 070: #define MSR_MTRRfix4K_E0000 0x0000026c 071: #define MSR_MTRRfix4K_E8000 0x0000026d 072: #define MSR_MTRRfix4K_F0000 0x0000026e 073: #define MSR_MTRRfix4K_F8000 0x0000026f 074: #define MSR_MTRRdefType 0x000002ff 075: 076: #define MSR_IA32_CR_PAT 0x00000277 077: 078: #define MSR_IA32_DEBUGCTLMSR 0x000001d9 079: #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 080: #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 081: #define MSR_IA32_LASTINTFROMIP 0x000001dd 082: #define MSR_IA32_LASTINTTOIP 0x000001de 083: 084: /* DEBUGCTLMSR bits (others vary by model): */ 085: #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 086: #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 087: #define DEBUGCTLMSR_TR (1UL << 6) 088: #define DEBUGCTLMSR_BTS (1UL << 7) 089: #define DEBUGCTLMSR_BTINT (1UL << 8) 090: #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 091: #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 092: #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 093: 094: #define MSR_IA32_MC0_CTL 0x00000400 095: #define MSR_IA32_MC0_STATUS 0x00000401 096: #define MSR_IA32_MC0_ADDR 0x00000402 097: #define MSR_IA32_MC0_MISC 0x00000403 098: 099: #define MSR_AMD64_MC0_MASK 0xc0010044 100: 101: #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 102: #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 103: #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 104: #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 105: 106: #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 107: 108: /* These are consecutive and not in the normal 4er MCE bank block */ 109: #define MSR_IA32_MC0_CTL2 0x00000280 110: #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 111: 112: #define MSR_P6_PERFCTR0 0x000000c1 113: #define MSR_P6_PERFCTR1 0x000000c2 114: #define MSR_P6_EVNTSEL0 0x00000186 115: #define MSR_P6_EVNTSEL1 0x00000187 116: 117: /* AMD64 MSRs. Not complete. See the architecture manual for a more 118: complete list. */ 119: 120: #define MSR_AMD64_PATCH_LEVEL 0x0000008b 121: #define MSR_AMD64_TSC_RATIO 0xc0000104 122: #define MSR_AMD64_NB_CFG 0xc001001f 123: #define MSR_AMD64_PATCH_LOADER 0xc0010020 124: #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 125: #define MSR_AMD64_OSVW_STATUS 0xc0010141 126: #define MSR_AMD64_DC_CFG 0xc0011022 127: #define MSR_AMD64_IBSFETCHCTL 0xc0011030 128: #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 129: #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 130: #define MSR_AMD64_IBSOPCTL 0xc0011033 131: #define MSR_AMD64_IBSOPRIP 0xc0011034 132: #define MSR_AMD64_IBSOPDATA 0xc0011035 133: #define MSR_AMD64_IBSOPDATA2 0xc0011036 134: #define MSR_AMD64_IBSOPDATA3 0xc0011037 135: #define MSR_AMD64_IBSDCLINAD 0xc0011038 136: #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 137: #define MSR_AMD64_IBSCTL 0xc001103a 138: #define MSR_AMD64_IBSBRTARGET 0xc001103b 139: 140: /* Fam 15h MSRs */ 141: #define MSR_F15H_PERF_CTL 0xc0010200 142: #define MSR_F15H_PERF_CTR 0xc0010201 143: 144: /* Fam 10h MSRs */ 145: #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 146: #define FAM10H_MMIO_CONF_ENABLE (1<<0) 147: #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 148: #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 149: #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 150: #define FAM10H_MMIO_CONF_BASE_SHIFT 20 151: #define MSR_FAM10H_NODE_ID 0xc001100c 152: 153: /* K8 MSRs */ 154: #define MSR_K8_TOP_MEM1 0xc001001a 155: #define MSR_K8_TOP_MEM2 0xc001001d 156: #define MSR_K8_SYSCFG 0xc0010010 157: #define MSR_K8_INT_PENDING_MSG 0xc0010055 158: /* C1E active bits in int pending message */ 159: #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 160: #define MSR_K8_TSEG_ADDR 0xc0010112 161: #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 162: #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 163: #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 164: 165: /* K7 MSRs */ 166: #define MSR_K7_EVNTSEL0 0xc0010000 167: #define MSR_K7_PERFCTR0 0xc0010004 168: #define MSR_K7_EVNTSEL1 0xc0010001 169: #define MSR_K7_PERFCTR1 0xc0010005 170: #define MSR_K7_EVNTSEL2 0xc0010002 171: #define MSR_K7_PERFCTR2 0xc0010006 172: #define MSR_K7_EVNTSEL3 0xc0010003 173: #define MSR_K7_PERFCTR3 0xc0010007 174: #define MSR_K7_CLK_CTL 0xc001001b 175: #define MSR_K7_HWCR 0xc0010015 176: #define MSR_K7_FID_VID_CTL 0xc0010041 177: #define MSR_K7_FID_VID_STATUS 0xc0010042 178: 179: /* K6 MSRs */ 180: #define MSR_K6_WHCR 0xc0000082 181: #define MSR_K6_UWCCR 0xc0000085 182: #define MSR_K6_EPMR 0xc0000086 183: #define MSR_K6_PSOR 0xc0000087 184: #define MSR_K6_PFIR 0xc0000088 185: 186: /* Centaur-Hauls/IDT defined MSRs. */ 187: #define MSR_IDT_FCR1 0x00000107 188: #define MSR_IDT_FCR2 0x00000108 189: #define MSR_IDT_FCR3 0x00000109 190: #define MSR_IDT_FCR4 0x0000010a 191: 192: #define MSR_IDT_MCR0 0x00000110 193: #define MSR_IDT_MCR1 0x00000111 194: #define MSR_IDT_MCR2 0x00000112 195: #define MSR_IDT_MCR3 0x00000113 196: #define MSR_IDT_MCR4 0x00000114 197: #define MSR_IDT_MCR5 0x00000115 198: #define MSR_IDT_MCR6 0x00000116 199: #define MSR_IDT_MCR7 0x00000117 200: #define MSR_IDT_MCR_CTRL 0x00000120 201: 202: /* VIA Cyrix defined MSRs*/ 203: #define MSR_VIA_FCR 0x00001107 204: #define MSR_VIA_LONGHAUL 0x0000110a 205: #define MSR_VIA_RNG 0x0000110b 206: #define MSR_VIA_BCR2 0x00001147 207: 208: /* Transmeta defined MSRs */ 209: #define MSR_TMTA_LONGRUN_CTRL 0x80868010 210: #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 211: #define MSR_TMTA_LRTI_READOUT 0x80868018 212: #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 213: 214: /* Intel defined MSRs. */ 215: #define MSR_IA32_P5_MC_ADDR 0x00000000 216: #define MSR_IA32_P5_MC_TYPE 0x00000001 217: #define MSR_IA32_TSC 0x00000010 218: #define MSR_IA32_PLATFORM_ID 0x00000017 219: #define MSR_IA32_EBL_CR_POWERON 0x0000002a 220: #define MSR_EBC_FREQUENCY_ID 0x0000002c 221: #define MSR_IA32_FEATURE_CONTROL 0x0000003a 222: 223: #define FEATURE_CONTROL_LOCKED (1<<0) 224: #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 225: #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 226: 227: #define MSR_IA32_APICBASE 0x0000001b 228: #define MSR_IA32_APICBASE_BSP (1<<8) 229: #define MSR_IA32_APICBASE_ENABLE (1<<11) 230: #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 231: 232: #define MSR_IA32_TSCDEADLINE 0x000006e0 233: 234: #define MSR_IA32_UCODE_WRITE 0x00000079 235: #define MSR_IA32_UCODE_REV 0x0000008b 236: 237: #define MSR_IA32_PERF_STATUS 0x00000198 238: #define MSR_IA32_PERF_CTL 0x00000199 239: 240: #define MSR_IA32_MPERF 0x000000e7 241: #define MSR_IA32_APERF 0x000000e8 242: 243: #define MSR_IA32_THERM_CONTROL 0x0000019a 244: #define MSR_IA32_THERM_INTERRUPT 0x0000019b 245: 246: #define THERM_INT_HIGH_ENABLE (1 << 0) 247: #define THERM_INT_LOW_ENABLE (1 << 1) 248: #define THERM_INT_PLN_ENABLE (1 << 24) 249: 250: #define MSR_IA32_THERM_STATUS 0x0000019c 251: 252: #define THERM_STATUS_PROCHOT (1 << 0) 253: #define THERM_STATUS_POWER_LIMIT (1 << 10) 254: 255: #define MSR_THERM2_CTL 0x0000019d 256: 257: #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 258: 259: #define MSR_IA32_MISC_ENABLE 0x000001a0 260: 261: #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 262: 263: #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 264: #define ENERGY_PERF_BIAS_PERFORMANCE 0 265: #define ENERGY_PERF_BIAS_NORMAL 6 266: #define ENERGY_PERF_BIAS_POWERSAVE 15 267: 268: #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 269: 270: #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 271: #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 272: 273: #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 274: 275: #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 276: #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 277: #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 278: 279: /* Thermal Thresholds Support */ 280: #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 281: #define THERM_SHIFT_THRESHOLD0 8 282: #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 283: #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 284: #define THERM_SHIFT_THRESHOLD1 16 285: #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 286: #define THERM_STATUS_THRESHOLD0 (1 << 6) 287: #define THERM_LOG_THRESHOLD0 (1 << 7) 288: #define THERM_STATUS_THRESHOLD1 (1 << 8) 289: #define THERM_LOG_THRESHOLD1 (1 << 9) 290: 291: /* MISC_ENABLE bits: architectural */ 292: #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 293: #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 294: #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 295: #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 296: #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 297: #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 298: #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 299: #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 300: #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 301: #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 302: 303: /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 304: #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 305: #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 306: #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 307: #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 308: #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 309: #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 310: #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 311: #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 312: #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 313: #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 314: #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 315: #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 316: #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 317: #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 318: #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 319: 320: /* P4/Xeon+ specific */ 321: #define MSR_IA32_MCG_EAX 0x00000180 322: #define MSR_IA32_MCG_EBX 0x00000181 323: #define MSR_IA32_MCG_ECX 0x00000182 324: #define MSR_IA32_MCG_EDX 0x00000183 325: #define MSR_IA32_MCG_ESI 0x00000184 326: #define MSR_IA32_MCG_EDI 0x00000185 327: #define MSR_IA32_MCG_EBP 0x00000186 328: #define MSR_IA32_MCG_ESP 0x00000187 329: #define MSR_IA32_MCG_EFLAGS 0x00000188 330: #define MSR_IA32_MCG_EIP 0x00000189 331: #define MSR_IA32_MCG_RESERVED 0x0000018a 332: 333: /* Pentium IV performance counter MSRs */ 334: #define MSR_P4_BPU_PERFCTR0 0x00000300 335: #define MSR_P4_BPU_PERFCTR1 0x00000301 336: #define MSR_P4_BPU_PERFCTR2 0x00000302 337: #define MSR_P4_BPU_PERFCTR3 0x00000303 338: #define MSR_P4_MS_PERFCTR0 0x00000304 339: #define MSR_P4_MS_PERFCTR1 0x00000305 340: #define MSR_P4_MS_PERFCTR2 0x00000306 341: #define MSR_P4_MS_PERFCTR3 0x00000307 342: #define MSR_P4_FLAME_PERFCTR0 0x00000308 343: #define MSR_P4_FLAME_PERFCTR1 0x00000309 344: #define MSR_P4_FLAME_PERFCTR2 0x0000030a 345: #define MSR_P4_FLAME_PERFCTR3 0x0000030b 346: #define MSR_P4_IQ_PERFCTR0 0x0000030c 347: #define MSR_P4_IQ_PERFCTR1 0x0000030d 348: #define MSR_P4_IQ_PERFCTR2 0x0000030e 349: #define MSR_P4_IQ_PERFCTR3 0x0000030f 350: #define MSR_P4_IQ_PERFCTR4 0x00000310 351: #define MSR_P4_IQ_PERFCTR5 0x00000311 352: #define MSR_P4_BPU_CCCR0 0x00000360 353: #define MSR_P4_BPU_CCCR1 0x00000361 354: #define MSR_P4_BPU_CCCR2 0x00000362 355: #define MSR_P4_BPU_CCCR3 0x00000363 356: #define MSR_P4_MS_CCCR0 0x00000364 357: #define MSR_P4_MS_CCCR1 0x00000365 358: #define MSR_P4_MS_CCCR2 0x00000366 359: #define MSR_P4_MS_CCCR3 0x00000367 360: #define MSR_P4_FLAME_CCCR0 0x00000368 361: #define MSR_P4_FLAME_CCCR1 0x00000369 362: #define MSR_P4_FLAME_CCCR2 0x0000036a 363: #define MSR_P4_FLAME_CCCR3 0x0000036b 364: #define MSR_P4_IQ_CCCR0 0x0000036c 365: #define MSR_P4_IQ_CCCR1 0x0000036d 366: #define MSR_P4_IQ_CCCR2 0x0000036e 367: #define MSR_P4_IQ_CCCR3 0x0000036f 368: #define MSR_P4_IQ_CCCR4 0x00000370 369: #define MSR_P4_IQ_CCCR5 0x00000371 370: #define MSR_P4_ALF_ESCR0 0x000003ca 371: #define MSR_P4_ALF_ESCR1 0x000003cb 372: #define MSR_P4_BPU_ESCR0 0x000003b2 373: #define MSR_P4_BPU_ESCR1 0x000003b3 374: #define MSR_P4_BSU_ESCR0 0x000003a0 375: #define MSR_P4_BSU_ESCR1 0x000003a1 376: #define MSR_P4_CRU_ESCR0 0x000003b8 377: #define MSR_P4_CRU_ESCR1 0x000003b9 378: #define MSR_P4_CRU_ESCR2 0x000003cc 379: #define MSR_P4_CRU_ESCR3 0x000003cd 380: #define MSR_P4_CRU_ESCR4 0x000003e0 381: #define MSR_P4_CRU_ESCR5 0x000003e1 382: #define MSR_P4_DAC_ESCR0 0x000003a8 383: #define MSR_P4_DAC_ESCR1 0x000003a9 384: #define MSR_P4_FIRM_ESCR0 0x000003a4 385: #define MSR_P4_FIRM_ESCR1 0x000003a5 386: #define MSR_P4_FLAME_ESCR0 0x000003a6 387: #define MSR_P4_FLAME_ESCR1 0x000003a7 388: #define MSR_P4_FSB_ESCR0 0x000003a2 389: #define MSR_P4_FSB_ESCR1 0x000003a3 390: #define MSR_P4_IQ_ESCR0 0x000003ba 391: #define MSR_P4_IQ_ESCR1 0x000003bb 392: #define MSR_P4_IS_ESCR0 0x000003b4 393: #define MSR_P4_IS_ESCR1 0x000003b5 394: #define MSR_P4_ITLB_ESCR0 0x000003b6 395: #define MSR_P4_ITLB_ESCR1 0x000003b7 396: #define MSR_P4_IX_ESCR0 0x000003c8 397: #define MSR_P4_IX_ESCR1 0x000003c9 398: #define MSR_P4_MOB_ESCR0 0x000003aa 399: #define MSR_P4_MOB_ESCR1 0x000003ab 400: #define MSR_P4_MS_ESCR0 0x000003c0 401: #define MSR_P4_MS_ESCR1 0x000003c1 402: #define MSR_P4_PMH_ESCR0 0x000003ac 403: #define MSR_P4_PMH_ESCR1 0x000003ad 404: #define MSR_P4_RAT_ESCR0 0x000003bc 405: #define MSR_P4_RAT_ESCR1 0x000003bd 406: #define MSR_P4_SAAT_ESCR0 0x000003ae 407: #define MSR_P4_SAAT_ESCR1 0x000003af 408: #define MSR_P4_SSU_ESCR0 0x000003be 409: #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 410: 411: #define MSR_P4_TBPU_ESCR0 0x000003c2 412: #define MSR_P4_TBPU_ESCR1 0x000003c3 413: #define MSR_P4_TC_ESCR0 0x000003c4 414: #define MSR_P4_TC_ESCR1 0x000003c5 415: #define MSR_P4_U2L_ESCR0 0x000003b0 416: #define MSR_P4_U2L_ESCR1 0x000003b1 417: 418: #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 419: 420: /* Intel Core-based CPU performance counters */ 421: #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 422: #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 423: #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 424: #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 425: #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 426: #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 427: #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 428: 429: /* Geode defined MSRs */ 430: #define MSR_GEODE_BUSCONT_CONF0 0x00001900 431: 432: /* Intel VT MSRs */ 433: #define MSR_IA32_VMX_BASIC 0x00000480 434: #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 435: #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 436: #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 437: #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 438: #define MSR_IA32_VMX_MISC 0x00000485 439: #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 440: #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 441: #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 442: #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 443: #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 444: #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 445: #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 446: #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 447: #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 448: #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 449: #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 450: 451: /* VMX_BASIC bits and bitmasks */ 452: #define VMX_BASIC_VMCS_SIZE_SHIFT 32 453: #define VMX_BASIC_64 0x0001000000000000LLU 454: #define VMX_BASIC_MEM_TYPE_SHIFT 50 455: #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 456: #define VMX_BASIC_MEM_TYPE_WB 6LLU 457: #define VMX_BASIC_INOUT 0x0040000000000000LLU 458: 459: /* AMD-V MSRs */ 460: 461: #define MSR_VM_CR 0xc0010114 462: #define MSR_VM_IGNNE 0xc0010115 463: #define MSR_VM_HSAVE_PA 0xc0010117 464: 465: #endif /* _ASM_X86_MSR_INDEX_H */ 466:
for client
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