---

---

---

001: #ifndef _ASM_X86_MCE_H
002: #define _ASM_X86_MCE_H
003: 
004: #include <linux/types.h>
005: #include <asm/ioctls.h>
006: 
007: /*
008:  * Machine Check support for x86
009:  */
010: 
011: /* MCG_CAP register defines */
012: #define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
013: #define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
014: #define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
015: #define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
016: #define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
017: #define MCG_EXT_CNT_SHIFT       16
018: #define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
019: #define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
020: 
021: /* MCG_STATUS register defines */
022: #define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
023: #define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
024: #define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
025: 
026: /* MCi_STATUS register defines */
027: #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
028: #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
029: #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
030: #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
031: #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
032: #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
033: #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
034: #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
035: #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
036: 
037: /* MCi_MISC register defines */
038: #define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
039: #define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
040: #define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
041: #define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
042: #define  MCI_MISC_ADDR_PHYS     2       /* physical address */
043: #define  MCI_MISC_ADDR_MEM      3       /* memory address */
044: #define  MCI_MISC_ADDR_GENERIC  7       /* generic */
045: 
046: /* CTL2 register defines */
047: #define MCI_CTL2_CMCI_EN                (1ULL << 30)
048: #define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
049: 
050: #define MCJ_CTX_MASK            3
051: #define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
052: #define MCJ_CTX_RANDOM          0    /* inject context: random */
053: #define MCJ_CTX_PROCESS         1    /* inject context: process */
054: #define MCJ_CTX_IRQ             2    /* inject context: IRQ */
055: #define MCJ_NMI_BROADCAST       4    /* do NMI broadcasting */
056: #define MCJ_EXCEPTION           8    /* raise as exception */
057: 
058: /* Fields are zero when not available */
059: struct mce {
060:         __u64 status;
061:         __u64 misc;
062:         __u64 addr;
063:         __u64 mcgstatus;
064:         __u64 ip;
065:         __u64 tsc;      /* cpu time stamp counter */
066:         __u64 time;     /* wall time_t when error was detected */
067:         __u8  cpuvendor;        /* cpu vendor as encoded in system.h */
068:         __u8  inject_flags;     /* software inject flags */
069:         __u16  pad;
070:         __u32 cpuid;    /* CPUID 1 EAX */
071:         __u8  cs;               /* code segment */
072:         __u8  bank;     /* machine check bank */
073:         __u8  cpu;      /* cpu number; obsolete; use extcpu now */
074:         __u8  finished;   /* entry is valid */
075:         __u32 extcpu;   /* linux cpu number that detected the error */
076:         __u32 socketid; /* CPU socket ID */
077:         __u32 apicid;   /* CPU initial apic ID */
078:         __u64 mcgcap;   /* MCGCAP MSR: machine check capabilities of CPU */
079:         __u64 aux0;     /* model specific */
080:         __u64 aux1;     /* model specific */
081: };
082: 
083: /*
084:  * This structure contains all data related to the MCE log.  Also
085:  * carries a signature to make it easier to find from external
086:  * debugging tools.  Each entry is only valid when its finished flag
087:  * is set.
088:  */
089: 
090: #define MCE_LOG_LEN 32
091: 
092: struct mce_log {
093:         char signature[12]; /* "MACHINECHECK" */
094:         unsigned len;       /* = MCE_LOG_LEN */
095:         unsigned next;
096:         unsigned flags;
097:         unsigned recordlen;     /* length of struct mce */
098:         struct mce entry[MCE_LOG_LEN];
099: };
100: 
101: #define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
102: 
103: #define MCE_LOG_SIGNATURE       "MACHINECHECK"
104: 
105: #define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
106: #define MCE_GET_LOG_LEN      _IOR('M', 2, int)
107: #define MCE_GETCLEAR_FLAGS   _IOR('M', 3, int)
108: 
109: /* Software defined banks */
110: #define MCE_EXTENDED_BANK       128
111: #define MCE_THERMAL_BANK        MCE_EXTENDED_BANK + 0
112: 
113: #define K8_MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)      /* MCE_AMD */
114: #define K8_MCE_THRESHOLD_BANK_0    (MCE_THRESHOLD_BASE + 0 * 9)
115: #define K8_MCE_THRESHOLD_BANK_1    (MCE_THRESHOLD_BASE + 1 * 9)
116: #define K8_MCE_THRESHOLD_BANK_2    (MCE_THRESHOLD_BASE + 2 * 9)
117: #define K8_MCE_THRESHOLD_BANK_3    (MCE_THRESHOLD_BASE + 3 * 9)
118: #define K8_MCE_THRESHOLD_BANK_4    (MCE_THRESHOLD_BASE + 4 * 9)
119: #define K8_MCE_THRESHOLD_BANK_5    (MCE_THRESHOLD_BASE + 5 * 9)
120: #define K8_MCE_THRESHOLD_DRAM_ECC  (MCE_THRESHOLD_BANK_4 + 0)
121: 
122: 
123: #endif /* _ASM_X86_MCE_H */
124: 

---

---

---