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001: /*
002:  * include/linux/serial_reg.h
003:  *
004:  * Copyright (C) 1992, 1994 by Theodore Ts'o.
005:  * 
006:  * Redistribution of this file is permitted under the terms of the GNU 
007:  * Public License (GPL)
008:  * 
009:  * These are the UART port assignments, expressed as offsets from the base
010:  * register.  These assignments should hold for any serial port based on
011:  * a 8250, 16450, or 16550(A).
012:  */
013: 
014: #ifndef _LINUX_SERIAL_REG_H
015: #define _LINUX_SERIAL_REG_H
016: 
017: /*
018:  * DLAB=0
019:  */
020: #define UART_RX         0       /* In:  Receive buffer */
021: #define UART_TX         0       /* Out: Transmit buffer */
022: 
023: #define UART_IER        1       /* Out: Interrupt Enable Register */
024: #define UART_IER_MSI            0x08 /* Enable Modem status interrupt */
025: #define UART_IER_RLSI           0x04 /* Enable receiver line status interrupt */
026: #define UART_IER_THRI           0x02 /* Enable Transmitter holding register int. */
027: #define UART_IER_RDI            0x01 /* Enable receiver data interrupt */
028: /*
029:  * Sleep mode for ST16650 and TI16750.  For the ST16650, EFR[4]=1
030:  */
031: #define UART_IERX_SLEEP         0x10 /* Enable sleep mode */
032: 
033: #define UART_IIR        2       /* In:  Interrupt ID Register */
034: #define UART_IIR_NO_INT         0x01 /* No interrupts pending */
035: #define UART_IIR_ID             0x06 /* Mask for the interrupt ID */
036: #define UART_IIR_MSI            0x00 /* Modem status interrupt */
037: #define UART_IIR_THRI           0x02 /* Transmitter holding register empty */
038: #define UART_IIR_RDI            0x04 /* Receiver data interrupt */
039: #define UART_IIR_RLSI           0x06 /* Receiver line status interrupt */
040: 
041: #define UART_IIR_BUSY           0x07 /* DesignWare APB Busy Detect */
042: 
043: #define UART_FCR        2       /* Out: FIFO Control Register */
044: #define UART_FCR_ENABLE_FIFO    0x01 /* Enable the FIFO */
045: #define UART_FCR_CLEAR_RCVR     0x02 /* Clear the RCVR FIFO */
046: #define UART_FCR_CLEAR_XMIT     0x04 /* Clear the XMIT FIFO */
047: #define UART_FCR_DMA_SELECT     0x08 /* For DMA applications */
048: /*
049:  * Note: The FIFO trigger levels are chip specific:
050:  *      RX:76 = 00  01  10  11  TX:54 = 00  01  10  11
051:  * PC16550D:     1   4   8  14          xx  xx  xx  xx
052:  * TI16C550A:    1   4   8  14          xx  xx  xx  xx
053:  * TI16C550C:    1   4   8  14          xx  xx  xx  xx
054:  * ST16C550:     1   4   8  14          xx  xx  xx  xx
055:  * ST16C650:     8  16  24  28          16   8  24  30  PORT_16650V2
056:  * NS16C552:     1   4   8  14          xx  xx  xx  xx
057:  * ST16C654:     8  16  56  60           8  16  32  56  PORT_16654
058:  * TI16C750:     1  16  32  56          xx  xx  xx  xx  PORT_16750
059:  * TI16C752:     8  16  56  60           8  16  32  56
060:  * Tegra:        1   4   8  14          16   8   4   1  PORT_TEGRA
061:  */
062: #define UART_FCR_R_TRIG_00      0x00
063: #define UART_FCR_R_TRIG_01      0x40
064: #define UART_FCR_R_TRIG_10      0x80
065: #define UART_FCR_R_TRIG_11      0xc0
066: #define UART_FCR_T_TRIG_00      0x00
067: #define UART_FCR_T_TRIG_01      0x10
068: #define UART_FCR_T_TRIG_10      0x20
069: #define UART_FCR_T_TRIG_11      0x30
070: 
071: #define UART_FCR_TRIGGER_MASK   0xC0 /* Mask for the FIFO trigger range */
072: #define UART_FCR_TRIGGER_1      0x00 /* Mask for trigger set at 1 */
073: #define UART_FCR_TRIGGER_4      0x40 /* Mask for trigger set at 4 */
074: #define UART_FCR_TRIGGER_8      0x80 /* Mask for trigger set at 8 */
075: #define UART_FCR_TRIGGER_14     0xC0 /* Mask for trigger set at 14 */
076: /* 16650 definitions */
077: #define UART_FCR6_R_TRIGGER_8   0x00 /* Mask for receive trigger set at 1 */
078: #define UART_FCR6_R_TRIGGER_16  0x40 /* Mask for receive trigger set at 4 */
079: #define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
080: #define UART_FCR6_R_TRIGGER_28  0xC0 /* Mask for receive trigger set at 14 */
081: #define UART_FCR6_T_TRIGGER_16  0x00 /* Mask for transmit trigger set at 16 */
082: #define UART_FCR6_T_TRIGGER_8   0x10 /* Mask for transmit trigger set at 8 */
083: #define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
084: #define UART_FCR6_T_TRIGGER_30  0x30 /* Mask for transmit trigger set at 30 */
085: #define UART_FCR7_64BYTE        0x20 /* Go into 64 byte mode (TI16C750) */
086: 
087: #define UART_LCR        3       /* Out: Line Control Register */
088: /*
089:  * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 
090:  * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
091:  */
092: #define UART_LCR_DLAB           0x80 /* Divisor latch access bit */
093: #define UART_LCR_SBC            0x40 /* Set break control */
094: #define UART_LCR_SPAR           0x20 /* Stick parity (?) */
095: #define UART_LCR_EPAR           0x10 /* Even parity select */
096: #define UART_LCR_PARITY         0x08 /* Parity Enable */
097: #define UART_LCR_STOP           0x04 /* Stop bits: 0=1 bit, 1=2 bits */
098: #define UART_LCR_WLEN5          0x00 /* Wordlength: 5 bits */
099: #define UART_LCR_WLEN6          0x01 /* Wordlength: 6 bits */
100: #define UART_LCR_WLEN7          0x02 /* Wordlength: 7 bits */
101: #define UART_LCR_WLEN8          0x03 /* Wordlength: 8 bits */
102: 
103: /*
104:  * Access to some registers depends on register access / configuration
105:  * mode.
106:  */
107: #define UART_LCR_CONF_MODE_A    UART_LCR_DLAB   /* Configutation mode A */
108: #define UART_LCR_CONF_MODE_B    0xBF            /* Configutation mode B */
109: 
110: #define UART_MCR        4       /* Out: Modem Control Register */
111: #define UART_MCR_CLKSEL         0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
112: #define UART_MCR_TCRTLR         0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
113: #define UART_MCR_XONANY         0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
114: #define UART_MCR_AFE            0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
115: #define UART_MCR_LOOP           0x10 /* Enable loopback test mode */
116: #define UART_MCR_OUT2           0x08 /* Out2 complement */
117: #define UART_MCR_OUT1           0x04 /* Out1 complement */
118: #define UART_MCR_RTS            0x02 /* RTS complement */
119: #define UART_MCR_DTR            0x01 /* DTR complement */
120: 
121: #define UART_LSR        5       /* In:  Line Status Register */
122: #define UART_LSR_FIFOE          0x80 /* Fifo error */
123: #define UART_LSR_TEMT           0x40 /* Transmitter empty */
124: #define UART_LSR_THRE           0x20 /* Transmit-hold-register empty */
125: #define UART_LSR_BI             0x10 /* Break interrupt indicator */
126: #define UART_LSR_FE             0x08 /* Frame error indicator */
127: #define UART_LSR_PE             0x04 /* Parity error indicator */
128: #define UART_LSR_OE             0x02 /* Overrun error indicator */
129: #define UART_LSR_DR             0x01 /* Receiver data ready */
130: #define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */
131: 
132: #define UART_MSR        6       /* In:  Modem Status Register */
133: #define UART_MSR_DCD            0x80 /* Data Carrier Detect */
134: #define UART_MSR_RI             0x40 /* Ring Indicator */
135: #define UART_MSR_DSR            0x20 /* Data Set Ready */
136: #define UART_MSR_CTS            0x10 /* Clear to Send */
137: #define UART_MSR_DDCD           0x08 /* Delta DCD */
138: #define UART_MSR_TERI           0x04 /* Trailing edge ring indicator */
139: #define UART_MSR_DDSR           0x02 /* Delta DSR */
140: #define UART_MSR_DCTS           0x01 /* Delta CTS */
141: #define UART_MSR_ANY_DELTA      0x0F /* Any of the delta bits! */
142: 
143: #define UART_SCR        7       /* I/O: Scratch Register */
144: 
145: /*
146:  * DLAB=1
147:  */
148: #define UART_DLL        0       /* Out: Divisor Latch Low */
149: #define UART_DLM        1       /* Out: Divisor Latch High */
150: 
151: /*
152:  * LCR=0xBF (or DLAB=1 for 16C660)
153:  */
154: #define UART_EFR        2       /* I/O: Extended Features Register */
155: #define UART_XR_EFR     9       /* I/O: Extended Features Register (XR17D15x) */
156: #define UART_EFR_CTS            0x80 /* CTS flow control */
157: #define UART_EFR_RTS            0x40 /* RTS flow control */
158: #define UART_EFR_SCD            0x20 /* Special character detect */
159: #define UART_EFR_ECB            0x10 /* Enhanced control bit */
160: /*
161:  * the low four bits control software flow control
162:  */
163: 
164: /*
165:  * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
166:  */
167: #define UART_XON1       4       /* I/O: Xon character 1 */
168: #define UART_XON2       5       /* I/O: Xon character 2 */
169: #define UART_XOFF1      6       /* I/O: Xoff character 1 */
170: #define UART_XOFF2      7       /* I/O: Xoff character 2 */
171: 
172: /*
173:  * EFR[4]=1 MCR[6]=1, TI16C752
174:  */
175: #define UART_TI752_TCR  6       /* I/O: transmission control register */
176: #define UART_TI752_TLR  7       /* I/O: trigger level register */
177: 
178: /*
179:  * LCR=0xBF, XR16C85x
180:  */
181: #define UART_TRG        0       /* FCTR bit 7 selects Rx or Tx
182:                                  * In: Fifo count
183:                                  * Out: Fifo custom trigger levels */
184: /*
185:  * These are the definitions for the Programmable Trigger Register
186:  */
187: #define UART_TRG_1              0x01
188: #define UART_TRG_4              0x04
189: #define UART_TRG_8              0x08
190: #define UART_TRG_16             0x10
191: #define UART_TRG_32             0x20
192: #define UART_TRG_64             0x40
193: #define UART_TRG_96             0x60
194: #define UART_TRG_120            0x78
195: #define UART_TRG_128            0x80
196: 
197: #define UART_FCTR       1       /* Feature Control Register */
198: #define UART_FCTR_RTS_NODELAY   0x00  /* RTS flow control delay */
199: #define UART_FCTR_RTS_4DELAY    0x01
200: #define UART_FCTR_RTS_6DELAY    0x02
201: #define UART_FCTR_RTS_8DELAY    0x03
202: #define UART_FCTR_IRDA          0x04  /* IrDa data encode select */
203: #define UART_FCTR_TX_INT        0x08  /* Tx interrupt type select */
204: #define UART_FCTR_TRGA          0x00  /* Tx/Rx 550 trigger table select */
205: #define UART_FCTR_TRGB          0x10  /* Tx/Rx 650 trigger table select */
206: #define UART_FCTR_TRGC          0x20  /* Tx/Rx 654 trigger table select */
207: #define UART_FCTR_TRGD          0x30  /* Tx/Rx 850 programmable trigger select */
208: #define UART_FCTR_SCR_SWAP      0x40  /* Scratch pad register swap */
209: #define UART_FCTR_RX            0x00  /* Programmable trigger mode select */
210: #define UART_FCTR_TX            0x80  /* Programmable trigger mode select */
211: 
212: /*
213:  * LCR=0xBF, FCTR[6]=1
214:  */
215: #define UART_EMSR       7       /* Extended Mode Select Register */
216: #define UART_EMSR_FIFO_COUNT    0x01  /* Rx/Tx select */
217: #define UART_EMSR_ALT_COUNT     0x02  /* Alternating count select */
218: 
219: /*
220:  * The Intel XScale on-chip UARTs define these bits
221:  */
222: #define UART_IER_DMAE   0x80    /* DMA Requests Enable */
223: #define UART_IER_UUE    0x40    /* UART Unit Enable */
224: #define UART_IER_NRZE   0x20    /* NRZ coding Enable */
225: #define UART_IER_RTOIE  0x10    /* Receiver Time Out Interrupt Enable */
226: 
227: #define UART_IIR_TOD    0x08    /* Character Timeout Indication Detected */
228: 
229: #define UART_FCR_PXAR1  0x00    /* receive FIFO threshold = 1 */
230: #define UART_FCR_PXAR8  0x40    /* receive FIFO threshold = 8 */
231: #define UART_FCR_PXAR16 0x80    /* receive FIFO threshold = 16 */
232: #define UART_FCR_PXAR32 0xc0    /* receive FIFO threshold = 32 */
233: 
234: /*
235:  * Intel MID on-chip HSU (High Speed UART) defined bits
236:  */
237: #define UART_FCR_HSU_64_1B      0x00    /* receive FIFO treshold = 1 */
238: #define UART_FCR_HSU_64_16B     0x40    /* receive FIFO treshold = 16 */
239: #define UART_FCR_HSU_64_32B     0x80    /* receive FIFO treshold = 32 */
240: #define UART_FCR_HSU_64_56B     0xc0    /* receive FIFO treshold = 56 */
241: 
242: #define UART_FCR_HSU_16_1B      0x00    /* receive FIFO treshold = 1 */
243: #define UART_FCR_HSU_16_4B      0x40    /* receive FIFO treshold = 4 */
244: #define UART_FCR_HSU_16_8B      0x80    /* receive FIFO treshold = 8 */
245: #define UART_FCR_HSU_16_14B     0xc0    /* receive FIFO treshold = 14 */
246: 
247: #define UART_FCR_HSU_64B_FIFO   0x20    /* chose 64 bytes FIFO */
248: #define UART_FCR_HSU_16B_FIFO   0x00    /* chose 16 bytes FIFO */
249: 
250: #define UART_FCR_HALF_EMPT_TXI  0x00    /* trigger TX_EMPT IRQ for half empty */
251: #define UART_FCR_FULL_EMPT_TXI  0x08    /* trigger TX_EMPT IRQ for full empty */
252: 
253: /*
254:  * These register definitions are for the 16C950
255:  */
256: #define UART_ASR        0x01    /* Additional Status Register */
257: #define UART_RFL        0x03    /* Receiver FIFO level */
258: #define UART_TFL        0x04    /* Transmitter FIFO level */
259: #define UART_ICR        0x05    /* Index Control Register */
260: 
261: /* The 16950 ICR registers */
262: #define UART_ACR        0x00    /* Additional Control Register */
263: #define UART_CPR        0x01    /* Clock Prescalar Register */
264: #define UART_TCR        0x02    /* Times Clock Register */
265: #define UART_CKS        0x03    /* Clock Select Register */
266: #define UART_TTL        0x04    /* Transmitter Interrupt Trigger Level */
267: #define UART_RTL        0x05    /* Receiver Interrupt Trigger Level */
268: #define UART_FCL        0x06    /* Flow Control Level Lower */
269: #define UART_FCH        0x07    /* Flow Control Level Higher */
270: #define UART_ID1        0x08    /* ID #1 */
271: #define UART_ID2        0x09    /* ID #2 */
272: #define UART_ID3        0x0A    /* ID #3 */
273: #define UART_REV        0x0B    /* Revision */
274: #define UART_CSR        0x0C    /* Channel Software Reset */
275: #define UART_NMR        0x0D    /* Nine-bit Mode Register */
276: #define UART_CTR        0xFF
277: 
278: /*
279:  * The 16C950 Additional Control Register
280:  */
281: #define UART_ACR_RXDIS  0x01    /* Receiver disable */
282: #define UART_ACR_TXDIS  0x02    /* Transmitter disable */
283: #define UART_ACR_DSRFC  0x04    /* DSR Flow Control */
284: #define UART_ACR_TLENB  0x20    /* 950 trigger levels enable */
285: #define UART_ACR_ICRRD  0x40    /* ICR Read enable */
286: #define UART_ACR_ASREN  0x80    /* Additional status enable */
287: 
288: 
289: 
290: /*
291:  * These definitions are for the RSA-DV II/S card, from
292:  *
293:  * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
294:  */
295: 
296: #define UART_RSA_BASE (-8)
297: 
298: #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
299: 
300: #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
301: #define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
302: #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
303: #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
304: 
305: #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
306: 
307: #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
308: #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
309: #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
310: #define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
311: #define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
312: 
313: #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
314: 
315: #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
316: #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
317: #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
318: #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
319: #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
320: #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
321: #define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
322: #define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
323: 
324: #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
325: 
326: #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
327: 
328: #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
329: 
330: #define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
331: 
332: /*
333:  * The RSA DSV/II board has two fixed clock frequencies.  One is the
334:  * standard rate, and the other is 8 times faster.
335:  */
336: #define SERIAL_RSA_BAUD_BASE (921600)
337: #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
338: 
339: /*
340:  * Extra serial register definitions for the internal UARTs
341:  * in TI OMAP processors.
342:  */
343: #define UART_OMAP_MDR1          0x08    /* Mode definition register */
344: #define UART_OMAP_MDR2          0x09    /* Mode definition register 2 */
345: #define UART_OMAP_SCR           0x10    /* Supplementary control register */
346: #define UART_OMAP_SSR           0x11    /* Supplementary status register */
347: #define UART_OMAP_EBLR          0x12    /* BOF length register */
348: #define UART_OMAP_OSC_12M_SEL   0x13    /* OMAP1510 12MHz osc select */
349: #define UART_OMAP_MVER          0x14    /* Module version register */
350: #define UART_OMAP_SYSC          0x15    /* System configuration register */
351: #define UART_OMAP_SYSS          0x16    /* System status register */
352: #define UART_OMAP_WER           0x17    /* Wake-up enable register */
353: 
354: /*
355:  * These are the definitions for the MDR1 register
356:  */
357: #define UART_OMAP_MDR1_16X_MODE         0x00    /* UART 16x mode */
358: #define UART_OMAP_MDR1_SIR_MODE         0x01    /* SIR mode */
359: #define UART_OMAP_MDR1_16X_ABAUD_MODE   0x02    /* UART 16x auto-baud */
360: #define UART_OMAP_MDR1_13X_MODE         0x03    /* UART 13x mode */
361: #define UART_OMAP_MDR1_MIR_MODE         0x04    /* MIR mode */
362: #define UART_OMAP_MDR1_FIR_MODE         0x05    /* FIR mode */
363: #define UART_OMAP_MDR1_CIR_MODE         0x06    /* CIR mode */
364: #define UART_OMAP_MDR1_DISABLE          0x07    /* Disable (default state) */
365: 
366: #endif /* _LINUX_SERIAL_REG_H */
367: 
368: 

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