hdlcdrv.h
001: 
002: 
003: 
004: 
005: 
006: 
007: #ifndef _HDLCDRV_H
008: #define _HDLCDRV_H
009: 
010: 
011: 
012: 
013: 
014: 
015: struct hdlcdrv_params {
016:         int iobase;
017:         int irq;
018:         int dma;
019:         int dma2;
020:         int seriobase;
021:         int pariobase;
022:         int midiiobase;
023: };      
024: 
025: struct hdlcdrv_channel_params {
026:         int tx_delay;  
027:         int tx_tail;   
028:         int slottime;  
029:         int ppersist;  
030:         int fulldup;   
031:                        
032: };      
033: 
034: struct hdlcdrv_old_channel_state {
035:         int ptt;
036:         int dcd;
037:         int ptt_keyed;
038: };
039: 
040: struct hdlcdrv_channel_state {
041:         int ptt;
042:         int dcd;
043:         int ptt_keyed;
044:         unsigned long tx_packets;
045:         unsigned long tx_errors;
046:         unsigned long rx_packets;
047:         unsigned long rx_errors;
048: };
049: 
050: struct hdlcdrv_ioctl {
051:         int cmd;
052:         union {
053:                 struct hdlcdrv_params mp;
054:                 struct hdlcdrv_channel_params cp;
055:                 struct hdlcdrv_channel_state cs;
056:                 struct hdlcdrv_old_channel_state ocs;
057:                 unsigned int calibrate;
058:                 unsigned char bits;
059:                 char modename[128];
060:                 char drivername[32];
061:         } data;
062: };
063: 
064: 
065: 
066: 
067: 
068: 
069: #define HDLCDRVCTL_GETMODEMPAR       0
070: #define HDLCDRVCTL_SETMODEMPAR       1
071: #define HDLCDRVCTL_MODEMPARMASK      2  
072: #define HDLCDRVCTL_GETCHANNELPAR    10
073: #define HDLCDRVCTL_SETCHANNELPAR    11
074: #define HDLCDRVCTL_OLDGETSTAT       20
075: #define HDLCDRVCTL_CALIBRATE        21
076: #define HDLCDRVCTL_GETSTAT          22
077: 
078: 
079: 
080: 
081: #define HDLCDRVCTL_GETSAMPLES       30
082: #define HDLCDRVCTL_GETBITS          31
083: 
084: 
085: 
086: 
087: #define HDLCDRVCTL_GETMODE          40
088: #define HDLCDRVCTL_SETMODE          41
089: #define HDLCDRVCTL_MODELIST         42
090: #define HDLCDRVCTL_DRIVERNAME       43
091: 
092: 
093: 
094: 
095: #define HDLCDRV_PARMASK_IOBASE      (1<<0)
096: #define HDLCDRV_PARMASK_IRQ         (1<<1)
097: #define HDLCDRV_PARMASK_DMA         (1<<2)
098: #define HDLCDRV_PARMASK_DMA2        (1<<3)
099: #define HDLCDRV_PARMASK_SERIOBASE   (1<<4)
100: #define HDLCDRV_PARMASK_PARIOBASE   (1<<5)
101: #define HDLCDRV_PARMASK_MIDIIOBASE  (1<<6)
102: 
103: 
104: 
105: 
106: 
107: 
108: #endif 
109: 
110: 
111: 
      
      
      
      
   
      
      
         
            
            © Andrew Scott 2006 -
            2025, 
            All Rights Reserved