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001: /* $Revision: 3.0 $$Date: 1998/11/02 14:20:59 $
002:  * linux/include/linux/cyclades.h
003:  *
004:  * This file was initially written by
005:  * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by
006:  * Ivan Passos <ivan@cyclades.com>.
007:  *
008:  * This file contains the general definitions for the cyclades.c driver
009:  *$Log: cyclades.h,v $
010:  *Revision 3.1  2002/01/29 11:36:16  henrique
011:  *added throttle field on struct cyclades_port to indicate whether the
012:  *port is throttled or not
013:  *
014:  *Revision 3.1  2000/04/19 18:52:52  ivan
015:  *converted address fields to unsigned long and added fields for physical
016:  *addresses on cyclades_card structure;
017:  *
018:  *Revision 3.0  1998/11/02 14:20:59  ivan
019:  *added nports field on cyclades_card structure;
020:  *
021:  *Revision 2.5  1998/08/03 16:57:01  ivan
022:  *added cyclades_idle_stats structure;
023:  * 
024:  *Revision 2.4  1998/06/01 12:09:53  ivan
025:  *removed closing_wait2 from cyclades_port structure;
026:  *
027:  *Revision 2.3  1998/03/16 18:01:12  ivan
028:  *changes in the cyclades_port structure to get it closer to the 
029:  *standard serial port structure;
030:  *added constants for new ioctls;
031:  *
032:  *Revision 2.2  1998/02/17 16:50:00  ivan
033:  *changes in the cyclades_port structure (addition of shutdown_wait and 
034:  *chip_rev variables);
035:  *added constants for new ioctls and for CD1400 rev. numbers.
036:  *
037:  *Revision 2.1  1997/10/24 16:03:00  ivan
038:  *added rflow (which allows enabling the CD1400 special flow control 
039:  *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to 
040:  *cyclades_port structure;
041:  *added Alpha support
042:  *
043:  *Revision 2.0  1997/06/30 10:30:00  ivan
044:  *added some new doorbell command constants related to IOCTLW and
045:  *UART error signaling
046:  *
047:  *Revision 1.8  1997/06/03 15:30:00  ivan
048:  *added constant ZFIRM_HLT
049:  *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin)
050:  *
051:  *Revision 1.7  1997/03/26 10:30:00  daniel
052:  *new entries at the end of cyclades_port struct to reallocate
053:  *variables illegally allocated within card memory.
054:  *
055:  *Revision 1.6  1996/09/09 18:35:30  bentson
056:  *fold in changes for Cyclom-Z -- including structures for
057:  *communicating with board as well modest changes to original
058:  *structures to support new features.
059:  *
060:  *Revision 1.5  1995/11/13 21:13:31  bentson
061:  *changes suggested by Michael Chastain <mec@duracef.shout.net>
062:  *to support use of this file in non-kernel applications
063:  *
064:  *
065:  */
066: 
067: #ifndef _LINUX_CYCLADES_H
068: #define _LINUX_CYCLADES_H
069: 
070: #include <linux/types.h>
071: 
072: struct cyclades_monitor {
073:         unsigned long           int_count;
074:         unsigned long           char_count;
075:         unsigned long           char_max;
076:         unsigned long           char_last;
077: };
078: 
079: /*
080:  * These stats all reflect activity since the device was last initialized.
081:  * (i.e., since the port was opened with no other processes already having it
082:  * open)
083:  */
084: struct cyclades_idle_stats {
085:     __kernel_time_t in_use;     /* Time device has been in use (secs) */
086:     __kernel_time_t recv_idle;  /* Time since last char received (secs) */
087:     __kernel_time_t xmit_idle;  /* Time since last char transmitted (secs) */
088:     unsigned long  recv_bytes;  /* Bytes received */
089:     unsigned long  xmit_bytes;  /* Bytes transmitted */
090:     unsigned long  overruns;    /* Input overruns */
091:     unsigned long  frame_errs;  /* Input framing errors */
092:     unsigned long  parity_errs; /* Input parity errors */
093: };
094: 
095: #define CYCLADES_MAGIC  0x4359
096: 
097: #define CYGETMON                0x435901
098: #define CYGETTHRESH             0x435902
099: #define CYSETTHRESH             0x435903
100: #define CYGETDEFTHRESH          0x435904
101: #define CYSETDEFTHRESH          0x435905
102: #define CYGETTIMEOUT            0x435906
103: #define CYSETTIMEOUT            0x435907
104: #define CYGETDEFTIMEOUT         0x435908
105: #define CYSETDEFTIMEOUT         0x435909
106: #define CYSETRFLOW              0x43590a
107: #define CYGETRFLOW              0x43590b
108: #define CYSETRTSDTR_INV         0x43590c
109: #define CYGETRTSDTR_INV         0x43590d
110: #define CYZSETPOLLCYCLE         0x43590e
111: #define CYZGETPOLLCYCLE         0x43590f
112: #define CYGETCD1400VER          0x435910
113: #define CYSETWAIT               0x435912
114: #define CYGETWAIT               0x435913
115: 
116: /*************** CYCLOM-Z ADDITIONS ***************/
117: 
118: #define CZIOC           ('M' << 8)
119: #define CZ_NBOARDS      (CZIOC|0xfa)
120: #define CZ_BOOT_START   (CZIOC|0xfb)
121: #define CZ_BOOT_DATA    (CZIOC|0xfc)
122: #define CZ_BOOT_END     (CZIOC|0xfd)
123: #define CZ_TEST         (CZIOC|0xfe)
124: 
125: #define CZ_DEF_POLL     (HZ/25)
126: 
127: #define MAX_BOARD       4       /* Max number of boards */
128: #define MAX_DEV         256     /* Max number of ports total */
129: #define CYZ_MAX_SPEED   921600
130: 
131: #define CYZ_FIFO_SIZE   16
132: 
133: #define CYZ_BOOT_NWORDS 0x100
134: struct CYZ_BOOT_CTRL {
135:         unsigned short  nboard;
136:         int             status[MAX_BOARD];
137:         int             nchannel[MAX_BOARD];
138:         int             fw_rev[MAX_BOARD];
139:         unsigned long   offset;
140:         unsigned long   data[CYZ_BOOT_NWORDS];
141: };
142: 
143: 
144: #ifndef DP_WINDOW_SIZE
145: /*
146:  *      Memory Window Sizes
147:  */
148: 
149: #define DP_WINDOW_SIZE          (0x00080000)    /* window size 512 Kb */
150: #define ZE_DP_WINDOW_SIZE       (0x00100000)    /* window size 1 Mb (Ze and
151:                                                   8Zo V.2 */
152: #define CTRL_WINDOW_SIZE        (0x00000080)    /* runtime regs 128 bytes */
153: 
154: /*
155:  *      CUSTOM_REG - Cyclom-Z/PCI Custom Registers Set. The driver
156:  *      normally will access only interested on the fpga_id, fpga_version,
157:  *      start_cpu and stop_cpu.
158:  */
159: 
160: struct  CUSTOM_REG {
161:         __u32   fpga_id;                /* FPGA Identification Register */
162:         __u32   fpga_version;           /* FPGA Version Number Register */
163:         __u32   cpu_start;              /* CPU start Register (write) */
164:         __u32   cpu_stop;               /* CPU stop Register (write) */
165:         __u32   misc_reg;               /* Miscellaneous Register */
166:         __u32   idt_mode;               /* IDT mode Register */
167:         __u32   uart_irq_status;        /* UART IRQ status Register */
168:         __u32   clear_timer0_irq;       /* Clear timer interrupt Register */
169:         __u32   clear_timer1_irq;       /* Clear timer interrupt Register */
170:         __u32   clear_timer2_irq;       /* Clear timer interrupt Register */
171:         __u32   test_register;          /* Test Register */
172:         __u32   test_count;             /* Test Count Register */
173:         __u32   timer_select;           /* Timer select register */
174:         __u32   pr_uart_irq_status;     /* Prioritized UART IRQ stat Reg */
175:         __u32   ram_wait_state;         /* RAM wait-state Register */
176:         __u32   uart_wait_state;        /* UART wait-state Register */
177:         __u32   timer_wait_state;       /* timer wait-state Register */
178:         __u32   ack_wait_state;         /* ACK wait State Register */
179: };
180: 
181: /*
182:  *      RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime
183:  *      registers. This structure can be used to access the 9060 registers
184:  *      (memory mapped).
185:  */
186: 
187: struct RUNTIME_9060 {
188:         __u32   loc_addr_range; /* 00h - Local Address Range */
189:         __u32   loc_addr_base;  /* 04h - Local Address Base */
190:         __u32   loc_arbitr;     /* 08h - Local Arbitration */
191:         __u32   endian_descr;   /* 0Ch - Big/Little Endian Descriptor */
192:         __u32   loc_rom_range;  /* 10h - Local ROM Range */
193:         __u32   loc_rom_base;   /* 14h - Local ROM Base */
194:         __u32   loc_bus_descr;  /* 18h - Local Bus descriptor */
195:         __u32   loc_range_mst;  /* 1Ch - Local Range for Master to PCI */
196:         __u32   loc_base_mst;   /* 20h - Local Base for Master PCI */
197:         __u32   loc_range_io;   /* 24h - Local Range for Master IO */
198:         __u32   pci_base_mst;   /* 28h - PCI Base for Master PCI */
199:         __u32   pci_conf_io;    /* 2Ch - PCI configuration for Master IO */
200:         __u32   filler1;        /* 30h */
201:         __u32   filler2;        /* 34h */
202:         __u32   filler3;        /* 38h */
203:         __u32   filler4;        /* 3Ch */
204:         __u32   mail_box_0;     /* 40h - Mail Box 0 */
205:         __u32   mail_box_1;     /* 44h - Mail Box 1 */
206:         __u32   mail_box_2;     /* 48h - Mail Box 2 */
207:         __u32   mail_box_3;     /* 4Ch - Mail Box 3 */
208:         __u32   filler5;        /* 50h */
209:         __u32   filler6;        /* 54h */
210:         __u32   filler7;        /* 58h */
211:         __u32   filler8;        /* 5Ch */
212:         __u32   pci_doorbell;   /* 60h - PCI to Local Doorbell */
213:         __u32   loc_doorbell;   /* 64h - Local to PCI Doorbell */
214:         __u32   intr_ctrl_stat; /* 68h - Interrupt Control/Status */
215:         __u32   init_ctrl;      /* 6Ch - EEPROM control, Init Control, etc */
216: };
217: 
218: /* Values for the Local Base Address re-map register */
219: 
220: #define WIN_RAM         0x00000001L     /* set the sliding window to RAM */
221: #define WIN_CREG        0x14000001L     /* set the window to custom Registers */
222: 
223: /* Values timer select registers */
224: 
225: #define TIMER_BY_1M     0x00            /* clock divided by 1M */
226: #define TIMER_BY_256K   0x01            /* clock divided by 256k */
227: #define TIMER_BY_128K   0x02            /* clock divided by 128k */
228: #define TIMER_BY_32K    0x03            /* clock divided by 32k */
229: 
230: /****************** ****************** *******************/
231: #endif
232: 
233: #ifndef ZFIRM_ID
234: /* #include "zfwint.h" */
235: /****************** ****************** *******************/
236: /*
237:  *      This file contains the definitions for interfacing with the
238:  *      Cyclom-Z ZFIRM Firmware.
239:  */
240: 
241: /* General Constant definitions */
242: 
243: #define MAX_CHAN        64              /* max number of channels per board */
244: 
245: /* firmware id structure (set after boot) */
246: 
247: #define ID_ADDRESS      0x00000180L     /* signature/pointer address */
248: #define ZFIRM_ID        0x5557465AL     /* ZFIRM/U signature */
249: #define ZFIRM_HLT       0x59505B5CL     /* ZFIRM needs external power supply */
250: #define ZFIRM_RST       0x56040674L     /* RST signal (due to FW reset) */
251: 
252: #define ZF_TINACT_DEF   1000            /* default inactivity timeout 
253:                                            (1000 ms) */
254: #define ZF_TINACT       ZF_TINACT_DEF
255: 
256: struct  FIRM_ID {
257:         __u32   signature;              /* ZFIRM/U signature */
258:         __u32   zfwctrl_addr;           /* pointer to ZFW_CTRL structure */
259: };
260: 
261: /* Op. System id */
262: 
263: #define C_OS_LINUX      0x00000030      /* generic Linux system */
264: 
265: /* channel op_mode */
266: 
267: #define C_CH_DISABLE    0x00000000      /* channel is disabled */
268: #define C_CH_TXENABLE   0x00000001      /* channel Tx enabled */
269: #define C_CH_RXENABLE   0x00000002      /* channel Rx enabled */
270: #define C_CH_ENABLE     0x00000003      /* channel Tx/Rx enabled */
271: #define C_CH_LOOPBACK   0x00000004      /* Loopback mode */
272: 
273: /* comm_parity - parity */
274: 
275: #define C_PR_NONE       0x00000000      /* None */
276: #define C_PR_ODD        0x00000001      /* Odd */
277: #define C_PR_EVEN       0x00000002      /* Even */
278: #define C_PR_MARK       0x00000004      /* Mark */
279: #define C_PR_SPACE      0x00000008      /* Space */
280: #define C_PR_PARITY     0x000000ff
281: 
282: #define C_PR_DISCARD    0x00000100      /* discard char with frame/par error */
283: #define C_PR_IGNORE     0x00000200      /* ignore frame/par error */
284: 
285: /* comm_data_l - data length and stop bits */
286: 
287: #define C_DL_CS5        0x00000001
288: #define C_DL_CS6        0x00000002
289: #define C_DL_CS7        0x00000004
290: #define C_DL_CS8        0x00000008
291: #define C_DL_CS         0x0000000f
292: #define C_DL_1STOP      0x00000010
293: #define C_DL_15STOP     0x00000020
294: #define C_DL_2STOP      0x00000040
295: #define C_DL_STOP       0x000000f0
296: 
297: /* interrupt enabling/status */
298: 
299: #define C_IN_DISABLE    0x00000000      /* zero, disable interrupts */
300: #define C_IN_TXBEMPTY   0x00000001      /* tx buffer empty */
301: #define C_IN_TXLOWWM    0x00000002      /* tx buffer below LWM */
302: #define C_IN_RXHIWM     0x00000010      /* rx buffer above HWM */
303: #define C_IN_RXNNDT     0x00000020      /* rx no new data timeout */
304: #define C_IN_MDCD       0x00000100      /* modem DCD change */
305: #define C_IN_MDSR       0x00000200      /* modem DSR change */
306: #define C_IN_MRI        0x00000400      /* modem RI change */
307: #define C_IN_MCTS       0x00000800      /* modem CTS change */
308: #define C_IN_RXBRK      0x00001000      /* Break received */
309: #define C_IN_PR_ERROR   0x00002000      /* parity error */
310: #define C_IN_FR_ERROR   0x00004000      /* frame error */
311: #define C_IN_OVR_ERROR  0x00008000      /* overrun error */
312: #define C_IN_RXOFL      0x00010000      /* RX buffer overflow */
313: #define C_IN_IOCTLW     0x00020000      /* I/O control w/ wait */
314: #define C_IN_MRTS       0x00040000      /* modem RTS drop */
315: #define C_IN_ICHAR      0x00080000
316:  
317: /* flow control */
318: 
319: #define C_FL_OXX        0x00000001      /* output Xon/Xoff flow control */
320: #define C_FL_IXX        0x00000002      /* output Xon/Xoff flow control */
321: #define C_FL_OIXANY     0x00000004      /* output Xon/Xoff (any xon) */
322: #define C_FL_SWFLOW     0x0000000f
323: 
324: /* flow status */
325: 
326: #define C_FS_TXIDLE     0x00000000      /* no Tx data in the buffer or UART */
327: #define C_FS_SENDING    0x00000001      /* UART is sending data */
328: #define C_FS_SWFLOW     0x00000002      /* Tx is stopped by received Xoff */
329: 
330: /* rs_control/rs_status RS-232 signals */
331: 
332: #define C_RS_PARAM      0x80000000      /* Indicates presence of parameter in 
333:                                            IOCTLM command */
334: #define C_RS_RTS        0x00000001      /* RTS */
335: #define C_RS_DTR        0x00000004      /* DTR */
336: #define C_RS_DCD        0x00000100      /* CD */
337: #define C_RS_DSR        0x00000200      /* DSR */
338: #define C_RS_RI         0x00000400      /* RI */
339: #define C_RS_CTS        0x00000800      /* CTS */
340: 
341: /* commands Host <-> Board */
342: 
343: #define C_CM_RESET      0x01            /* reset/flush buffers */
344: #define C_CM_IOCTL      0x02            /* re-read CH_CTRL */
345: #define C_CM_IOCTLW     0x03            /* re-read CH_CTRL, intr when done */
346: #define C_CM_IOCTLM     0x04            /* RS-232 outputs change */
347: #define C_CM_SENDXOFF   0x10            /* send Xoff */
348: #define C_CM_SENDXON    0x11            /* send Xon */
349: #define C_CM_CLFLOW     0x12            /* Clear flow control (resume) */
350: #define C_CM_SENDBRK    0x41            /* send break */
351: #define C_CM_INTBACK    0x42            /* Interrupt back */
352: #define C_CM_SET_BREAK  0x43            /* Tx break on */
353: #define C_CM_CLR_BREAK  0x44            /* Tx break off */
354: #define C_CM_CMD_DONE   0x45            /* Previous command done */
355: #define C_CM_INTBACK2   0x46            /* Alternate Interrupt back */
356: #define C_CM_TINACT     0x51            /* set inactivity detection */
357: #define C_CM_IRQ_ENBL   0x52            /* enable generation of interrupts */
358: #define C_CM_IRQ_DSBL   0x53            /* disable generation of interrupts */
359: #define C_CM_ACK_ENBL   0x54            /* enable acknowledged interrupt mode */
360: #define C_CM_ACK_DSBL   0x55            /* disable acknowledged intr mode */
361: #define C_CM_FLUSH_RX   0x56            /* flushes Rx buffer */
362: #define C_CM_FLUSH_TX   0x57            /* flushes Tx buffer */
363: #define C_CM_Q_ENABLE   0x58            /* enables queue access from the 
364:                                            driver */
365: #define C_CM_Q_DISABLE  0x59            /* disables queue access from the 
366:                                            driver */
367: 
368: #define C_CM_TXBEMPTY   0x60            /* Tx buffer is empty */
369: #define C_CM_TXLOWWM    0x61            /* Tx buffer low water mark */
370: #define C_CM_RXHIWM     0x62            /* Rx buffer high water mark */
371: #define C_CM_RXNNDT     0x63            /* rx no new data timeout */
372: #define C_CM_TXFEMPTY   0x64
373: #define C_CM_ICHAR      0x65
374: #define C_CM_MDCD       0x70            /* modem DCD change */
375: #define C_CM_MDSR       0x71            /* modem DSR change */
376: #define C_CM_MRI        0x72            /* modem RI change */
377: #define C_CM_MCTS       0x73            /* modem CTS change */
378: #define C_CM_MRTS       0x74            /* modem RTS drop */
379: #define C_CM_RXBRK      0x84            /* Break received */
380: #define C_CM_PR_ERROR   0x85            /* Parity error */
381: #define C_CM_FR_ERROR   0x86            /* Frame error */
382: #define C_CM_OVR_ERROR  0x87            /* Overrun error */
383: #define C_CM_RXOFL      0x88            /* RX buffer overflow */
384: #define C_CM_CMDERROR   0x90            /* command error */
385: #define C_CM_FATAL      0x91            /* fatal error */
386: #define C_CM_HW_RESET   0x92            /* reset board */
387: 
388: /*
389:  *      CH_CTRL - This per port structure contains all parameters
390:  *      that control an specific port. It can be seen as the
391:  *      configuration registers of a "super-serial-controller".
392:  */
393: 
394: struct CH_CTRL {
395:         __u32   op_mode;        /* operation mode */
396:         __u32   intr_enable;    /* interrupt masking */
397:         __u32   sw_flow;        /* SW flow control */
398:         __u32   flow_status;    /* output flow status */
399:         __u32   comm_baud;      /* baud rate  - numerically specified */
400:         __u32   comm_parity;    /* parity */
401:         __u32   comm_data_l;    /* data length/stop */
402:         __u32   comm_flags;     /* other flags */
403:         __u32   hw_flow;        /* HW flow control */
404:         __u32   rs_control;     /* RS-232 outputs */
405:         __u32   rs_status;      /* RS-232 inputs */
406:         __u32   flow_xon;       /* xon char */
407:         __u32   flow_xoff;      /* xoff char */
408:         __u32   hw_overflow;    /* hw overflow counter */
409:         __u32   sw_overflow;    /* sw overflow counter */
410:         __u32   comm_error;     /* frame/parity error counter */
411:         __u32 ichar;
412:         __u32 filler[7];
413: };
414: 
415: 
416: /*
417:  *      BUF_CTRL - This per channel structure contains
418:  *      all Tx and Rx buffer control for a given channel.
419:  */
420: 
421: struct  BUF_CTRL        {
422:         __u32   flag_dma;       /* buffers are in Host memory */
423:         __u32   tx_bufaddr;     /* address of the tx buffer */
424:         __u32   tx_bufsize;     /* tx buffer size */
425:         __u32   tx_threshold;   /* tx low water mark */
426:         __u32   tx_get;         /* tail index tx buf */
427:         __u32   tx_put;         /* head index tx buf */
428:         __u32   rx_bufaddr;     /* address of the rx buffer */
429:         __u32   rx_bufsize;     /* rx buffer size */
430:         __u32   rx_threshold;   /* rx high water mark */
431:         __u32   rx_get;         /* tail index rx buf */
432:         __u32   rx_put;         /* head index rx buf */
433:         __u32   filler[5];      /* filler to align structures */
434: };
435: 
436: /*
437:  *      BOARD_CTRL - This per board structure contains all global 
438:  *      control fields related to the board.
439:  */
440: 
441: struct BOARD_CTRL {
442: 
443:         /* static info provided by the on-board CPU */
444:         __u32   n_channel;      /* number of channels */
445:         __u32   fw_version;     /* firmware version */
446: 
447:         /* static info provided by the driver */
448:         __u32   op_system;      /* op_system id */
449:         __u32   dr_version;     /* driver version */
450: 
451:         /* board control area */
452:         __u32   inactivity;     /* inactivity control */
453: 
454:         /* host to FW commands */
455:         __u32   hcmd_channel;   /* channel number */
456:         __u32   hcmd_param;     /* pointer to parameters */
457: 
458:         /* FW to Host commands */
459:         __u32   fwcmd_channel;  /* channel number */
460:         __u32   fwcmd_param;    /* pointer to parameters */
461:         __u32   zf_int_queue_addr; /* offset for INT_QUEUE structure */
462: 
463:         /* filler so the structures are aligned */
464:         __u32   filler[6];
465: };
466: 
467: /* Host Interrupt Queue */
468: 
469: #define QUEUE_SIZE      (10*MAX_CHAN)
470: 
471: struct  INT_QUEUE {
472:         unsigned char   intr_code[QUEUE_SIZE];
473:         unsigned long   channel[QUEUE_SIZE];
474:         unsigned long   param[QUEUE_SIZE];
475:         unsigned long   put;
476:         unsigned long   get;
477: };
478: 
479: /*
480:  *      ZFW_CTRL - This is the data structure that includes all other
481:  *      data structures used by the Firmware.
482:  */
483:  
484: struct ZFW_CTRL {
485:         struct BOARD_CTRL       board_ctrl;
486:         struct CH_CTRL          ch_ctrl[MAX_CHAN];
487:         struct BUF_CTRL         buf_ctrl[MAX_CHAN];
488: };
489: 
490: /****************** ****************** *******************/
491: #endif
492: 
493: #endif /* _LINUX_CYCLADES_H */
494: 

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