Dr Andrew Scott
G7VAV
Senior Lecturer
School of Computing
and Communications
D35 InfoLab21
Lancaster University
Lancaster, LA1 4WA
United Kingdom
School of Computing
and Communications
D35 InfoLab21
Lancaster University
Lancaster, LA1 4WA
United Kingdom
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radeon_drm.h
001: /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 002: * 003: * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 004: * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 005: * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 006: * All rights reserved. 007: * 008: * Permission is hereby granted, free of charge, to any person obtaining a 009: * copy of this software and associated documentation files (the "Software"), 010: * to deal in the Software without restriction, including without limitation 011: * the rights to use, copy, modify, merge, publish, distribute, sublicense, 012: * and/or sell copies of the Software, and to permit persons to whom the 013: * Software is furnished to do so, subject to the following conditions: 014: * 015: * The above copyright notice and this permission notice (including the next 016: * paragraph) shall be included in all copies or substantial portions of the 017: * Software. 018: * 019: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 020: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 021: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 022: * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 023: * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 024: * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 025: * DEALINGS IN THE SOFTWARE. 026: * 027: * Authors: 028: * Kevin E. Martin <martin@valinux.com> 029: * Gareth Hughes <gareth@valinux.com> 030: * Keith Whitwell <keith@tungstengraphics.com> 031: */ 032: 033: #ifndef __RADEON_DRM_H__ 034: #define __RADEON_DRM_H__ 035: 036: #include <drm/drm.h> 037: 038: /* WARNING: If you change any of these defines, make sure to change the 039: * defines in the X server file (radeon_sarea.h) 040: */ 041: #ifndef __RADEON_SAREA_DEFINES__ 042: #define __RADEON_SAREA_DEFINES__ 043: 044: /* Old style state flags, required for sarea interface (1.1 and 1.2 045: * clears) and 1.2 drm_vertex2 ioctl. 046: */ 047: #define RADEON_UPLOAD_CONTEXT 0x00000001 048: #define RADEON_UPLOAD_VERTFMT 0x00000002 049: #define RADEON_UPLOAD_LINE 0x00000004 050: #define RADEON_UPLOAD_BUMPMAP 0x00000008 051: #define RADEON_UPLOAD_MASKS 0x00000010 052: #define RADEON_UPLOAD_VIEWPORT 0x00000020 053: #define RADEON_UPLOAD_SETUP 0x00000040 054: #define RADEON_UPLOAD_TCL 0x00000080 055: #define RADEON_UPLOAD_MISC 0x00000100 056: #define RADEON_UPLOAD_TEX0 0x00000200 057: #define RADEON_UPLOAD_TEX1 0x00000400 058: #define RADEON_UPLOAD_TEX2 0x00000800 059: #define RADEON_UPLOAD_TEX0IMAGES 0x00001000 060: #define RADEON_UPLOAD_TEX1IMAGES 0x00002000 061: #define RADEON_UPLOAD_TEX2IMAGES 0x00004000 062: #define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ 063: #define RADEON_REQUIRE_QUIESCENCE 0x00010000 064: #define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ 065: #define RADEON_UPLOAD_ALL 0x003effff 066: #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 067: 068: /* New style per-packet identifiers for use in cmd_buffer ioctl with 069: * the RADEON_EMIT_PACKET command. Comments relate new packets to old 070: * state bits and the packet size: 071: */ 072: #define RADEON_EMIT_PP_MISC 0 /* context/7 */ 073: #define RADEON_EMIT_PP_CNTL 1 /* context/3 */ 074: #define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ 075: #define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ 076: #define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ 077: #define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ 078: #define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ 079: #define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ 080: #define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ 081: #define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ 082: #define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ 083: #define RADEON_EMIT_RE_MISC 11 /* misc/1 */ 084: #define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ 085: #define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ 086: #define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ 087: #define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ 088: #define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ 089: #define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ 090: #define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ 091: #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ 092: #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ 093: #define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ 094: #define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ 095: #define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ 096: #define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ 097: #define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ 098: #define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ 099: #define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ 100: #define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ 101: #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ 102: #define R200_EMIT_TFACTOR_0 30 /* tf/7 */ 103: #define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ 104: #define R200_EMIT_VAP_CTL 32 /* vap/1 */ 105: #define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ 106: #define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ 107: #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ 108: #define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ 109: #define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ 110: #define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ 111: #define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ 112: #define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ 113: #define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ 114: #define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ 115: #define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ 116: #define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ 117: #define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ 118: #define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ 119: #define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ 120: #define R200_EMIT_VTE_CNTL 48 /* vte/1 */ 121: #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ 122: #define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ 123: #define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ 124: #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ 125: #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ 126: #define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ 127: #define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ 128: #define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ 129: #define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ 130: #define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ 131: #define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ 132: #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ 133: #define R200_EMIT_PP_CUBIC_FACES_0 61 134: #define R200_EMIT_PP_CUBIC_OFFSETS_0 62 135: #define R200_EMIT_PP_CUBIC_FACES_1 63 136: #define R200_EMIT_PP_CUBIC_OFFSETS_1 64 137: #define R200_EMIT_PP_CUBIC_FACES_2 65 138: #define R200_EMIT_PP_CUBIC_OFFSETS_2 66 139: #define R200_EMIT_PP_CUBIC_FACES_3 67 140: #define R200_EMIT_PP_CUBIC_OFFSETS_3 68 141: #define R200_EMIT_PP_CUBIC_FACES_4 69 142: #define R200_EMIT_PP_CUBIC_OFFSETS_4 70 143: #define R200_EMIT_PP_CUBIC_FACES_5 71 144: #define R200_EMIT_PP_CUBIC_OFFSETS_5 72 145: #define RADEON_EMIT_PP_TEX_SIZE_0 73 146: #define RADEON_EMIT_PP_TEX_SIZE_1 74 147: #define RADEON_EMIT_PP_TEX_SIZE_2 75 148: #define R200_EMIT_RB3D_BLENDCOLOR 76 149: #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 150: #define RADEON_EMIT_PP_CUBIC_FACES_0 78 151: #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 152: #define RADEON_EMIT_PP_CUBIC_FACES_1 80 153: #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 154: #define RADEON_EMIT_PP_CUBIC_FACES_2 82 155: #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 156: #define R200_EMIT_PP_TRI_PERF_CNTL 84 157: #define R200_EMIT_PP_AFS_0 85 158: #define R200_EMIT_PP_AFS_1 86 159: #define R200_EMIT_ATF_TFACTOR 87 160: #define R200_EMIT_PP_TXCTLALL_0 88 161: #define R200_EMIT_PP_TXCTLALL_1 89 162: #define R200_EMIT_PP_TXCTLALL_2 90 163: #define R200_EMIT_PP_TXCTLALL_3 91 164: #define R200_EMIT_PP_TXCTLALL_4 92 165: #define R200_EMIT_PP_TXCTLALL_5 93 166: #define R200_EMIT_VAP_PVS_CNTL 94 167: #define RADEON_MAX_STATE_PACKETS 95 168: 169: /* Commands understood by cmd_buffer ioctl. More can be added but 170: * obviously these can't be removed or changed: 171: */ 172: #define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ 173: #define RADEON_CMD_SCALARS 2 /* emit scalar data */ 174: #define RADEON_CMD_VECTORS 3 /* emit vector data */ 175: #define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ 176: #define RADEON_CMD_PACKET3 5 /* emit hw packet */ 177: #define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ 178: #define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ 179: #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: 180: * doesn't make the cpu wait, just 181: * the graphics hardware */ 182: #define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ 183: 184: typedef union { 185: int i; 186: struct { 187: unsigned char cmd_type, pad0, pad1, pad2; 188: } header; 189: struct { 190: unsigned char cmd_type, packet_id, pad0, pad1; 191: } packet; 192: struct { 193: unsigned char cmd_type, offset, stride, count; 194: } scalars; 195: struct { 196: unsigned char cmd_type, offset, stride, count; 197: } vectors; 198: struct { 199: unsigned char cmd_type, addr_lo, addr_hi, count; 200: } veclinear; 201: struct { 202: unsigned char cmd_type, buf_idx, pad0, pad1; 203: } dma; 204: struct { 205: unsigned char cmd_type, flags, pad0, pad1; 206: } wait; 207: } drm_radeon_cmd_header_t; 208: 209: #define RADEON_WAIT_2D 0x1 210: #define RADEON_WAIT_3D 0x2 211: 212: /* Allowed parameters for R300_CMD_PACKET3 213: */ 214: #define R300_CMD_PACKET3_CLEAR 0 215: #define R300_CMD_PACKET3_RAW 1 216: 217: /* Commands understood by cmd_buffer ioctl for R300. 218: * The interface has not been stabilized, so some of these may be removed 219: * and eventually reordered before stabilization. 220: */ 221: #define R300_CMD_PACKET0 1 222: #define R300_CMD_VPU 2 /* emit vertex program upload */ 223: #define R300_CMD_PACKET3 3 /* emit a packet3 */ 224: #define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ 225: #define R300_CMD_CP_DELAY 5 226: #define R300_CMD_DMA_DISCARD 6 227: #define R300_CMD_WAIT 7 228: # define R300_WAIT_2D 0x1 229: # define R300_WAIT_3D 0x2 230: /* these two defines are DOING IT WRONG - however 231: * we have userspace which relies on using these. 232: * The wait interface is backwards compat new 233: * code should use the NEW_WAIT defines below 234: * THESE ARE NOT BIT FIELDS 235: */ 236: # define R300_WAIT_2D_CLEAN 0x3 237: # define R300_WAIT_3D_CLEAN 0x4 238: 239: # define R300_NEW_WAIT_2D_3D 0x3 240: # define R300_NEW_WAIT_2D_2D_CLEAN 0x4 241: # define R300_NEW_WAIT_3D_3D_CLEAN 0x6 242: # define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 243: 244: #define R300_CMD_SCRATCH 8 245: #define R300_CMD_R500FP 9 246: 247: typedef union { 248: unsigned int u; 249: struct { 250: unsigned char cmd_type, pad0, pad1, pad2; 251: } header; 252: struct { 253: unsigned char cmd_type, count, reglo, reghi; 254: } packet0; 255: struct { 256: unsigned char cmd_type, count, adrlo, adrhi; 257: } vpu; 258: struct { 259: unsigned char cmd_type, packet, pad0, pad1; 260: } packet3; 261: struct { 262: unsigned char cmd_type, packet; 263: unsigned short count; /* amount of packet2 to emit */ 264: } delay; 265: struct { 266: unsigned char cmd_type, buf_idx, pad0, pad1; 267: } dma; 268: struct { 269: unsigned char cmd_type, flags, pad0, pad1; 270: } wait; 271: struct { 272: unsigned char cmd_type, reg, n_bufs, flags; 273: } scratch; 274: struct { 275: unsigned char cmd_type, count, adrlo, adrhi_flags; 276: } r500fp; 277: } drm_r300_cmd_header_t; 278: 279: #define RADEON_FRONT 0x1 280: #define RADEON_BACK 0x2 281: #define RADEON_DEPTH 0x4 282: #define RADEON_STENCIL 0x8 283: #define RADEON_CLEAR_FASTZ 0x80000000 284: #define RADEON_USE_HIERZ 0x40000000 285: #define RADEON_USE_COMP_ZBUF 0x20000000 286: 287: #define R500FP_CONSTANT_TYPE (1 << 1) 288: #define R500FP_CONSTANT_CLAMP (1 << 2) 289: 290: /* Primitive types 291: */ 292: #define RADEON_POINTS 0x1 293: #define RADEON_LINES 0x2 294: #define RADEON_LINE_STRIP 0x3 295: #define RADEON_TRIANGLES 0x4 296: #define RADEON_TRIANGLE_FAN 0x5 297: #define RADEON_TRIANGLE_STRIP 0x6 298: 299: /* Vertex/indirect buffer size 300: */ 301: #define RADEON_BUFFER_SIZE 65536 302: 303: /* Byte offsets for indirect buffer data 304: */ 305: #define RADEON_INDEX_PRIM_OFFSET 20 306: 307: #define RADEON_SCRATCH_REG_OFFSET 32 308: 309: #define R600_SCRATCH_REG_OFFSET 256 310: 311: #define RADEON_NR_SAREA_CLIPRECTS 12 312: 313: /* There are 2 heaps (local/GART). Each region within a heap is a 314: * minimum of 64k, and there are at most 64 of them per heap. 315: */ 316: #define RADEON_LOCAL_TEX_HEAP 0 317: #define RADEON_GART_TEX_HEAP 1 318: #define RADEON_NR_TEX_HEAPS 2 319: #define RADEON_NR_TEX_REGIONS 64 320: #define RADEON_LOG_TEX_GRANULARITY 16 321: 322: #define RADEON_MAX_TEXTURE_LEVELS 12 323: #define RADEON_MAX_TEXTURE_UNITS 3 324: 325: #define RADEON_MAX_SURFACES 8 326: 327: /* Blits have strict offset rules. All blit offset must be aligned on 328: * a 1K-byte boundary. 329: */ 330: #define RADEON_OFFSET_SHIFT 10 331: #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 332: #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 333: 334: #endif /* __RADEON_SAREA_DEFINES__ */ 335: 336: typedef struct { 337: unsigned int red; 338: unsigned int green; 339: unsigned int blue; 340: unsigned int alpha; 341: } radeon_color_regs_t; 342: 343: typedef struct { 344: /* Context state */ 345: unsigned int pp_misc; /* 0x1c14 */ 346: unsigned int pp_fog_color; 347: unsigned int re_solid_color; 348: unsigned int rb3d_blendcntl; 349: unsigned int rb3d_depthoffset; 350: unsigned int rb3d_depthpitch; 351: unsigned int rb3d_zstencilcntl; 352: 353: unsigned int pp_cntl; /* 0x1c38 */ 354: unsigned int rb3d_cntl; 355: unsigned int rb3d_coloroffset; 356: unsigned int re_width_height; 357: unsigned int rb3d_colorpitch; 358: unsigned int se_cntl; 359: 360: /* Vertex format state */ 361: unsigned int se_coord_fmt; /* 0x1c50 */ 362: 363: /* Line state */ 364: unsigned int re_line_pattern; /* 0x1cd0 */ 365: unsigned int re_line_state; 366: 367: unsigned int se_line_width; /* 0x1db8 */ 368: 369: /* Bumpmap state */ 370: unsigned int pp_lum_matrix; /* 0x1d00 */ 371: 372: unsigned int pp_rot_matrix_0; /* 0x1d58 */ 373: unsigned int pp_rot_matrix_1; 374: 375: /* Mask state */ 376: unsigned int rb3d_stencilrefmask; /* 0x1d7c */ 377: unsigned int rb3d_ropcntl; 378: unsigned int rb3d_planemask; 379: 380: /* Viewport state */ 381: unsigned int se_vport_xscale; /* 0x1d98 */ 382: unsigned int se_vport_xoffset; 383: unsigned int se_vport_yscale; 384: unsigned int se_vport_yoffset; 385: unsigned int se_vport_zscale; 386: unsigned int se_vport_zoffset; 387: 388: /* Setup state */ 389: unsigned int se_cntl_status; /* 0x2140 */ 390: 391: /* Misc state */ 392: unsigned int re_top_left; /* 0x26c0 */ 393: unsigned int re_misc; 394: } drm_radeon_context_regs_t; 395: 396: typedef struct { 397: /* Zbias state */ 398: unsigned int se_zbias_factor; /* 0x1dac */ 399: unsigned int se_zbias_constant; 400: } drm_radeon_context2_regs_t; 401: 402: /* Setup registers for each texture unit 403: */ 404: typedef struct { 405: unsigned int pp_txfilter; 406: unsigned int pp_txformat; 407: unsigned int pp_txoffset; 408: unsigned int pp_txcblend; 409: unsigned int pp_txablend; 410: unsigned int pp_tfactor; 411: unsigned int pp_border_color; 412: } drm_radeon_texture_regs_t; 413: 414: typedef struct { 415: unsigned int start; 416: unsigned int finish; 417: unsigned int prim:8; 418: unsigned int stateidx:8; 419: unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ 420: unsigned int vc_format; /* vertex format */ 421: } drm_radeon_prim_t; 422: 423: typedef struct { 424: drm_radeon_context_regs_t context; 425: drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 426: drm_radeon_context2_regs_t context2; 427: unsigned int dirty; 428: } drm_radeon_state_t; 429: 430: typedef struct { 431: /* The channel for communication of state information to the 432: * kernel on firing a vertex buffer with either of the 433: * obsoleted vertex/index ioctls. 434: */ 435: drm_radeon_context_regs_t context_state; 436: drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 437: unsigned int dirty; 438: unsigned int vertsize; 439: unsigned int vc_format; 440: 441: /* The current cliprects, or a subset thereof. 442: */ 443: struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; 444: unsigned int nbox; 445: 446: /* Counters for client-side throttling of rendering clients. 447: */ 448: unsigned int last_frame; 449: unsigned int last_dispatch; 450: unsigned int last_clear; 451: 452: struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 453: 1]; 454: unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 455: int ctx_owner; 456: int pfState; /* number of 3d windows (0,1,2ormore) */ 457: int pfCurrentPage; /* which buffer is being displayed? */ 458: int crtc2_base; /* CRTC2 frame offset */ 459: int tiling_enabled; /* set by drm, read by 2d + 3d clients */ 460: } drm_radeon_sarea_t; 461: 462: /* WARNING: If you change any of these defines, make sure to change the 463: * defines in the Xserver file (xf86drmRadeon.h) 464: * 465: * KW: actually it's illegal to change any of this (backwards compatibility). 466: */ 467: 468: /* Radeon specific ioctls 469: * The device specific ioctl range is 0x40 to 0x79. 470: */ 471: #define DRM_RADEON_CP_INIT 0x00 472: #define DRM_RADEON_CP_START 0x01 473: #define DRM_RADEON_CP_STOP 0x02 474: #define DRM_RADEON_CP_RESET 0x03 475: #define DRM_RADEON_CP_IDLE 0x04 476: #define DRM_RADEON_RESET 0x05 477: #define DRM_RADEON_FULLSCREEN 0x06 478: #define DRM_RADEON_SWAP 0x07 479: #define DRM_RADEON_CLEAR 0x08 480: #define DRM_RADEON_VERTEX 0x09 481: #define DRM_RADEON_INDICES 0x0A 482: #define DRM_RADEON_NOT_USED 483: #define DRM_RADEON_STIPPLE 0x0C 484: #define DRM_RADEON_INDIRECT 0x0D 485: #define DRM_RADEON_TEXTURE 0x0E 486: #define DRM_RADEON_VERTEX2 0x0F 487: #define DRM_RADEON_CMDBUF 0x10 488: #define DRM_RADEON_GETPARAM 0x11 489: #define DRM_RADEON_FLIP 0x12 490: #define DRM_RADEON_ALLOC 0x13 491: #define DRM_RADEON_FREE 0x14 492: #define DRM_RADEON_INIT_HEAP 0x15 493: #define DRM_RADEON_IRQ_EMIT 0x16 494: #define DRM_RADEON_IRQ_WAIT 0x17 495: #define DRM_RADEON_CP_RESUME 0x18 496: #define DRM_RADEON_SETPARAM 0x19 497: #define DRM_RADEON_SURF_ALLOC 0x1a 498: #define DRM_RADEON_SURF_FREE 0x1b 499: /* KMS ioctl */ 500: #define DRM_RADEON_GEM_INFO 0x1c 501: #define DRM_RADEON_GEM_CREATE 0x1d 502: #define DRM_RADEON_GEM_MMAP 0x1e 503: #define DRM_RADEON_GEM_PREAD 0x21 504: #define DRM_RADEON_GEM_PWRITE 0x22 505: #define DRM_RADEON_GEM_SET_DOMAIN 0x23 506: #define DRM_RADEON_GEM_WAIT_IDLE 0x24 507: #define DRM_RADEON_CS 0x26 508: #define DRM_RADEON_INFO 0x27 509: #define DRM_RADEON_GEM_SET_TILING 0x28 510: #define DRM_RADEON_GEM_GET_TILING 0x29 511: #define DRM_RADEON_GEM_BUSY 0x2a 512: 513: #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 514: #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) 515: #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 516: #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 517: #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 518: #define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) 519: #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 520: #define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) 521: #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 522: #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 523: #define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 524: #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 525: #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 526: #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 527: #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 528: #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 529: #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 530: #define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) 531: #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 532: #define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 533: #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 534: #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 535: #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 536: #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 537: #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 538: #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 539: #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) 540: /* KMS */ 541: #define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) 542: #define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) 543: #define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) 544: #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) 545: #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) 546: #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) 547: #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) 548: #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) 549: #define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) 550: #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) 551: #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) 552: #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) 553: 554: typedef struct drm_radeon_init { 555: enum { 556: RADEON_INIT_CP = 0x01, 557: RADEON_CLEANUP_CP = 0x02, 558: RADEON_INIT_R200_CP = 0x03, 559: RADEON_INIT_R300_CP = 0x04, 560: RADEON_INIT_R600_CP = 0x05 561: } func; 562: unsigned long sarea_priv_offset; 563: int is_pci; 564: int cp_mode; 565: int gart_size; 566: int ring_size; 567: int usec_timeout; 568: 569: unsigned int fb_bpp; 570: unsigned int front_offset, front_pitch; 571: unsigned int back_offset, back_pitch; 572: unsigned int depth_bpp; 573: unsigned int depth_offset, depth_pitch; 574: 575: unsigned long fb_offset; 576: unsigned long mmio_offset; 577: unsigned long ring_offset; 578: unsigned long ring_rptr_offset; 579: unsigned long buffers_offset; 580: unsigned long gart_textures_offset; 581: } drm_radeon_init_t; 582: 583: typedef struct drm_radeon_cp_stop { 584: int flush; 585: int idle; 586: } drm_radeon_cp_stop_t; 587: 588: typedef struct drm_radeon_fullscreen { 589: enum { 590: RADEON_INIT_FULLSCREEN = 0x01, 591: RADEON_CLEANUP_FULLSCREEN = 0x02 592: } func; 593: } drm_radeon_fullscreen_t; 594: 595: #define CLEAR_X1 0 596: #define CLEAR_Y1 1 597: #define CLEAR_X2 2 598: #define CLEAR_Y2 3 599: #define CLEAR_DEPTH 4 600: 601: typedef union drm_radeon_clear_rect { 602: float f[5]; 603: unsigned int ui[5]; 604: } drm_radeon_clear_rect_t; 605: 606: typedef struct drm_radeon_clear { 607: unsigned int flags; 608: unsigned int clear_color; 609: unsigned int clear_depth; 610: unsigned int color_mask; 611: unsigned int depth_mask; /* misnamed field: should be stencil */ 612: drm_radeon_clear_rect_t *depth_boxes; 613: } drm_radeon_clear_t; 614: 615: typedef struct drm_radeon_vertex { 616: int prim; 617: int idx; /* Index of vertex buffer */ 618: int count; /* Number of vertices in buffer */ 619: int discard; /* Client finished with buffer? */ 620: } drm_radeon_vertex_t; 621: 622: typedef struct drm_radeon_indices { 623: int prim; 624: int idx; 625: int start; 626: int end; 627: int discard; /* Client finished with buffer? */ 628: } drm_radeon_indices_t; 629: 630: /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices 631: * - allows multiple primitives and state changes in a single ioctl 632: * - supports driver change to emit native primitives 633: */ 634: typedef struct drm_radeon_vertex2 { 635: int idx; /* Index of vertex buffer */ 636: int discard; /* Client finished with buffer? */ 637: int nr_states; 638: drm_radeon_state_t *state; 639: int nr_prims; 640: drm_radeon_prim_t *prim; 641: } drm_radeon_vertex2_t; 642: 643: /* v1.3 - obsoletes drm_radeon_vertex2 644: * - allows arbitrarily large cliprect list 645: * - allows updating of tcl packet, vector and scalar state 646: * - allows memory-efficient description of state updates 647: * - allows state to be emitted without a primitive 648: * (for clears, ctx switches) 649: * - allows more than one dma buffer to be referenced per ioctl 650: * - supports tcl driver 651: * - may be extended in future versions with new cmd types, packets 652: */ 653: typedef struct drm_radeon_cmd_buffer { 654: int bufsz; 655: char *buf; 656: int nbox; 657: struct drm_clip_rect *boxes; 658: } drm_radeon_cmd_buffer_t; 659: 660: typedef struct drm_radeon_tex_image { 661: unsigned int x, y; /* Blit coordinates */ 662: unsigned int width, height; 663: const void *data; 664: } drm_radeon_tex_image_t; 665: 666: typedef struct drm_radeon_texture { 667: unsigned int offset; 668: int pitch; 669: int format; 670: int width; /* Texture image coordinates */ 671: int height; 672: drm_radeon_tex_image_t *image; 673: } drm_radeon_texture_t; 674: 675: typedef struct drm_radeon_stipple { 676: unsigned int *mask; 677: } drm_radeon_stipple_t; 678: 679: typedef struct drm_radeon_indirect { 680: int idx; 681: int start; 682: int end; 683: int discard; 684: } drm_radeon_indirect_t; 685: 686: /* enum for card type parameters */ 687: #define RADEON_CARD_PCI 0 688: #define RADEON_CARD_AGP 1 689: #define RADEON_CARD_PCIE 2 690: 691: /* 1.3: An ioctl to get parameters that aren't available to the 3d 692: * client any other way. 693: */ 694: #define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ 695: #define RADEON_PARAM_LAST_FRAME 2 696: #define RADEON_PARAM_LAST_DISPATCH 3 697: #define RADEON_PARAM_LAST_CLEAR 4 698: /* Added with DRM version 1.6. */ 699: #define RADEON_PARAM_IRQ_NR 5 700: #define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ 701: /* Added with DRM version 1.8. */ 702: #define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ 703: #define RADEON_PARAM_STATUS_HANDLE 8 704: #define RADEON_PARAM_SAREA_HANDLE 9 705: #define RADEON_PARAM_GART_TEX_HANDLE 10 706: #define RADEON_PARAM_SCRATCH_OFFSET 11 707: #define RADEON_PARAM_CARD_TYPE 12 708: #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ 709: #define RADEON_PARAM_FB_LOCATION 14 /* FB location */ 710: #define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ 711: #define RADEON_PARAM_DEVICE_ID 16 712: #define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ 713: 714: typedef struct drm_radeon_getparam { 715: int param; 716: void *value; 717: } drm_radeon_getparam_t; 718: 719: /* 1.6: Set up a memory manager for regions of shared memory: 720: */ 721: #define RADEON_MEM_REGION_GART 1 722: #define RADEON_MEM_REGION_FB 2 723: 724: typedef struct drm_radeon_mem_alloc { 725: int region; 726: int alignment; 727: int size; 728: int *region_offset; /* offset from start of fb or GART */ 729: } drm_radeon_mem_alloc_t; 730: 731: typedef struct drm_radeon_mem_free { 732: int region; 733: int region_offset; 734: } drm_radeon_mem_free_t; 735: 736: typedef struct drm_radeon_mem_init_heap { 737: int region; 738: int size; 739: int start; 740: } drm_radeon_mem_init_heap_t; 741: 742: /* 1.6: Userspace can request & wait on irq's: 743: */ 744: typedef struct drm_radeon_irq_emit { 745: int *irq_seq; 746: } drm_radeon_irq_emit_t; 747: 748: typedef struct drm_radeon_irq_wait { 749: int irq_seq; 750: } drm_radeon_irq_wait_t; 751: 752: /* 1.10: Clients tell the DRM where they think the framebuffer is located in 753: * the card's address space, via a new generic ioctl to set parameters 754: */ 755: 756: typedef struct drm_radeon_setparam { 757: unsigned int param; 758: __s64 value; 759: } drm_radeon_setparam_t; 760: 761: #define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ 762: #define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ 763: #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ 764: #define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ 765: #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ 766: #define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ 767: /* 1.14: Clients can allocate/free a surface 768: */ 769: typedef struct drm_radeon_surface_alloc { 770: unsigned int address; 771: unsigned int size; 772: unsigned int flags; 773: } drm_radeon_surface_alloc_t; 774: 775: typedef struct drm_radeon_surface_free { 776: unsigned int address; 777: } drm_radeon_surface_free_t; 778: 779: #define DRM_RADEON_VBLANK_CRTC1 1 780: #define DRM_RADEON_VBLANK_CRTC2 2 781: 782: /* 783: * Kernel modesetting world below. 784: */ 785: #define RADEON_GEM_DOMAIN_CPU 0x1 786: #define RADEON_GEM_DOMAIN_GTT 0x2 787: #define RADEON_GEM_DOMAIN_VRAM 0x4 788: 789: struct drm_radeon_gem_info { 790: uint64_t gart_size; 791: uint64_t vram_size; 792: uint64_t vram_visible; 793: }; 794: 795: #define RADEON_GEM_NO_BACKING_STORE 1 796: 797: struct drm_radeon_gem_create { 798: uint64_t size; 799: uint64_t alignment; 800: uint32_t handle; 801: uint32_t initial_domain; 802: uint32_t flags; 803: }; 804: 805: #define RADEON_TILING_MACRO 0x1 806: #define RADEON_TILING_MICRO 0x2 807: #define RADEON_TILING_SWAP_16BIT 0x4 808: #define RADEON_TILING_SWAP_32BIT 0x8 809: #define RADEON_TILING_SURFACE 0x10 /* this object requires a surface 810: * when mapped - i.e. front buffer */ 811: #define RADEON_TILING_MICRO_SQUARE 0x20 812: 813: struct drm_radeon_gem_set_tiling { 814: uint32_t handle; 815: uint32_t tiling_flags; 816: uint32_t pitch; 817: }; 818: 819: struct drm_radeon_gem_get_tiling { 820: uint32_t handle; 821: uint32_t tiling_flags; 822: uint32_t pitch; 823: }; 824: 825: struct drm_radeon_gem_mmap { 826: uint32_t handle; 827: uint32_t pad; 828: uint64_t offset; 829: uint64_t size; 830: uint64_t addr_ptr; 831: }; 832: 833: struct drm_radeon_gem_set_domain { 834: uint32_t handle; 835: uint32_t read_domains; 836: uint32_t write_domain; 837: }; 838: 839: struct drm_radeon_gem_wait_idle { 840: uint32_t handle; 841: uint32_t pad; 842: }; 843: 844: struct drm_radeon_gem_busy { 845: uint32_t handle; 846: uint32_t domain; 847: }; 848: 849: struct drm_radeon_gem_pread { 850: /** Handle for the object being read. */ 851: uint32_t handle; 852: uint32_t pad; 853: /** Offset into the object to read from */ 854: uint64_t offset; 855: /** Length of data to read */ 856: uint64_t size; 857: /** Pointer to write the data into. */ 858: /* void *, but pointers are not 32/64 compatible */ 859: uint64_t data_ptr; 860: }; 861: 862: struct drm_radeon_gem_pwrite { 863: /** Handle for the object being written to. */ 864: uint32_t handle; 865: uint32_t pad; 866: /** Offset into the object to write to */ 867: uint64_t offset; 868: /** Length of data to write */ 869: uint64_t size; 870: /** Pointer to read the data from. */ 871: /* void *, but pointers are not 32/64 compatible */ 872: uint64_t data_ptr; 873: }; 874: 875: #define RADEON_CHUNK_ID_RELOCS 0x01 876: #define RADEON_CHUNK_ID_IB 0x02 877: #define RADEON_CHUNK_ID_FLAGS 0x03 878: 879: /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ 880: #define RADEON_CS_KEEP_TILING_FLAGS 0x01 881: 882: struct drm_radeon_cs_chunk { 883: uint32_t chunk_id; 884: uint32_t length_dw; 885: uint64_t chunk_data; 886: }; 887: 888: struct drm_radeon_cs_reloc { 889: uint32_t handle; 890: uint32_t read_domains; 891: uint32_t write_domain; 892: uint32_t flags; 893: }; 894: 895: struct drm_radeon_cs { 896: uint32_t num_chunks; 897: uint32_t cs_id; 898: /* this points to uint64_t * which point to cs chunks */ 899: uint64_t chunks; 900: /* updates to the limits after this CS ioctl */ 901: uint64_t gart_limit; 902: uint64_t vram_limit; 903: }; 904: 905: #define RADEON_INFO_DEVICE_ID 0x00 906: #define RADEON_INFO_NUM_GB_PIPES 0x01 907: #define RADEON_INFO_NUM_Z_PIPES 0x02 908: #define RADEON_INFO_ACCEL_WORKING 0x03 909: #define RADEON_INFO_CRTC_FROM_ID 0x04 910: #define RADEON_INFO_ACCEL_WORKING2 0x05 911: #define RADEON_INFO_TILING_CONFIG 0x06 912: #define RADEON_INFO_WANT_HYPERZ 0x07 913: #define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ 914: #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ 915: #define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */ 916: #define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ 917: #define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */ 918: #define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ 919: 920: struct drm_radeon_info { 921: uint32_t request; 922: uint32_t pad; 923: uint64_t value; 924: }; 925: 926: #endif 927:
for client
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