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001: /* r128_drm.h -- Public header for the r128 driver -*- linux-c -*-
002:  * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
003:  */
004: /*
005:  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
006:  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
007:  * All rights reserved.
008:  *
009:  * Permission is hereby granted, free of charge, to any person obtaining a
010:  * copy of this software and associated documentation files (the "Software"),
011:  * to deal in the Software without restriction, including without limitation
012:  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
013:  * and/or sell copies of the Software, and to permit persons to whom the
014:  * Software is furnished to do so, subject to the following conditions:
015:  *
016:  * The above copyright notice and this permission notice (including the next
017:  * paragraph) shall be included in all copies or substantial portions of the
018:  * Software.
019:  *
020:  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
021:  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
022:  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
023:  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
024:  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
025:  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
026:  * DEALINGS IN THE SOFTWARE.
027:  *
028:  * Authors:
029:  *    Gareth Hughes <gareth@valinux.com>
030:  *    Kevin E. Martin <martin@valinux.com>
031:  */
032: 
033: #ifndef __R128_DRM_H__
034: #define __R128_DRM_H__
035: 
036: /* WARNING: If you change any of these defines, make sure to change the
037:  * defines in the X server file (r128_sarea.h)
038:  */
039: #ifndef __R128_SAREA_DEFINES__
040: #define __R128_SAREA_DEFINES__
041: 
042: /* What needs to be changed for the current vertex buffer?
043:  */
044: #define R128_UPLOAD_CONTEXT             0x001
045: #define R128_UPLOAD_SETUP               0x002
046: #define R128_UPLOAD_TEX0                0x004
047: #define R128_UPLOAD_TEX1                0x008
048: #define R128_UPLOAD_TEX0IMAGES          0x010
049: #define R128_UPLOAD_TEX1IMAGES          0x020
050: #define R128_UPLOAD_CORE                0x040
051: #define R128_UPLOAD_MASKS               0x080
052: #define R128_UPLOAD_WINDOW              0x100
053: #define R128_UPLOAD_CLIPRECTS           0x200   /* handled client-side */
054: #define R128_REQUIRE_QUIESCENCE         0x400
055: #define R128_UPLOAD_ALL                 0x7ff
056: 
057: #define R128_FRONT                      0x1
058: #define R128_BACK                       0x2
059: #define R128_DEPTH                      0x4
060: 
061: /* Primitive types
062:  */
063: #define R128_POINTS                     0x1
064: #define R128_LINES                      0x2
065: #define R128_LINE_STRIP                 0x3
066: #define R128_TRIANGLES                  0x4
067: #define R128_TRIANGLE_FAN               0x5
068: #define R128_TRIANGLE_STRIP             0x6
069: 
070: /* Vertex/indirect buffer size
071:  */
072: #define R128_BUFFER_SIZE                16384
073: 
074: /* Byte offsets for indirect buffer data
075:  */
076: #define R128_INDEX_PRIM_OFFSET          20
077: #define R128_HOSTDATA_BLIT_OFFSET       32
078: 
079: /* Keep these small for testing.
080:  */
081: #define R128_NR_SAREA_CLIPRECTS         12
082: 
083: /* There are 2 heaps (local/AGP).  Each region within a heap is a
084:  *  minimum of 64k, and there are at most 64 of them per heap.
085:  */
086: #define R128_LOCAL_TEX_HEAP             0
087: #define R128_AGP_TEX_HEAP               1
088: #define R128_NR_TEX_HEAPS               2
089: #define R128_NR_TEX_REGIONS             64
090: #define R128_LOG_TEX_GRANULARITY        16
091: 
092: #define R128_NR_CONTEXT_REGS            12
093: 
094: #define R128_MAX_TEXTURE_LEVELS         11
095: #define R128_MAX_TEXTURE_UNITS          2
096: 
097: #endif                          /* __R128_SAREA_DEFINES__ */
098: 
099: typedef struct {
100:         /* Context state - can be written in one large chunk */
101:         unsigned int dst_pitch_offset_c;
102:         unsigned int dp_gui_master_cntl_c;
103:         unsigned int sc_top_left_c;
104:         unsigned int sc_bottom_right_c;
105:         unsigned int z_offset_c;
106:         unsigned int z_pitch_c;
107:         unsigned int z_sten_cntl_c;
108:         unsigned int tex_cntl_c;
109:         unsigned int misc_3d_state_cntl_reg;
110:         unsigned int texture_clr_cmp_clr_c;
111:         unsigned int texture_clr_cmp_msk_c;
112:         unsigned int fog_color_c;
113: 
114:         /* Texture state */
115:         unsigned int tex_size_pitch_c;
116:         unsigned int constant_color_c;
117: 
118:         /* Setup state */
119:         unsigned int pm4_vc_fpu_setup;
120:         unsigned int setup_cntl;
121: 
122:         /* Mask state */
123:         unsigned int dp_write_mask;
124:         unsigned int sten_ref_mask_c;
125:         unsigned int plane_3d_mask_c;
126: 
127:         /* Window state */
128:         unsigned int window_xy_offset;
129: 
130:         /* Core state */
131:         unsigned int scale_3d_cntl;
132: } drm_r128_context_regs_t;
133: 
134: /* Setup registers for each texture unit
135:  */
136: typedef struct {
137:         unsigned int tex_cntl;
138:         unsigned int tex_combine_cntl;
139:         unsigned int tex_size_pitch;
140:         unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
141:         unsigned int tex_border_color;
142: } drm_r128_texture_regs_t;
143: 
144: typedef struct drm_r128_sarea {
145:         /* The channel for communication of state information to the kernel
146:          * on firing a vertex buffer.
147:          */
148:         drm_r128_context_regs_t context_state;
149:         drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
150:         unsigned int dirty;
151:         unsigned int vertsize;
152:         unsigned int vc_format;
153: 
154:         /* The current cliprects, or a subset thereof.
155:          */
156:         struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
157:         unsigned int nbox;
158: 
159:         /* Counters for client-side throttling of rendering clients.
160:          */
161:         unsigned int last_frame;
162:         unsigned int last_dispatch;
163: 
164:         struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
165:         unsigned int tex_age[R128_NR_TEX_HEAPS];
166:         int ctx_owner;
167:         int pfAllowPageFlip;    /* number of 3d windows (0,1,2 or more) */
168:         int pfCurrentPage;      /* which buffer is being displayed? */
169: } drm_r128_sarea_t;
170: 
171: /* WARNING: If you change any of these defines, make sure to change the
172:  * defines in the Xserver file (xf86drmR128.h)
173:  */
174: 
175: /* Rage 128 specific ioctls
176:  * The device specific ioctl range is 0x40 to 0x79.
177:  */
178: #define DRM_R128_INIT       0x00
179: #define DRM_R128_CCE_START  0x01
180: #define DRM_R128_CCE_STOP   0x02
181: #define DRM_R128_CCE_RESET  0x03
182: #define DRM_R128_CCE_IDLE   0x04
183: /* 0x05 not used */
184: #define DRM_R128_RESET      0x06
185: #define DRM_R128_SWAP       0x07
186: #define DRM_R128_CLEAR      0x08
187: #define DRM_R128_VERTEX     0x09
188: #define DRM_R128_INDICES    0x0a
189: #define DRM_R128_BLIT       0x0b
190: #define DRM_R128_DEPTH      0x0c
191: #define DRM_R128_STIPPLE    0x0d
192: /* 0x0e not used */
193: #define DRM_R128_INDIRECT   0x0f
194: #define DRM_R128_FULLSCREEN 0x10
195: #define DRM_R128_CLEAR2     0x11
196: #define DRM_R128_GETPARAM   0x12
197: #define DRM_R128_FLIP       0x13
198: 
199: #define DRM_IOCTL_R128_INIT       DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
200: #define DRM_IOCTL_R128_CCE_START  DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_START)
201: #define DRM_IOCTL_R128_CCE_STOP   DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
202: #define DRM_IOCTL_R128_CCE_RESET  DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
203: #define DRM_IOCTL_R128_CCE_IDLE   DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
204: /* 0x05 not used */
205: #define DRM_IOCTL_R128_RESET      DRM_IO(  DRM_COMMAND_BASE + DRM_R128_RESET)
206: #define DRM_IOCTL_R128_SWAP       DRM_IO(  DRM_COMMAND_BASE + DRM_R128_SWAP)
207: #define DRM_IOCTL_R128_CLEAR      DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
208: #define DRM_IOCTL_R128_VERTEX     DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
209: #define DRM_IOCTL_R128_INDICES    DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
210: #define DRM_IOCTL_R128_BLIT       DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
211: #define DRM_IOCTL_R128_DEPTH      DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
212: #define DRM_IOCTL_R128_STIPPLE    DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
213: /* 0x0e not used */
214: #define DRM_IOCTL_R128_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
215: #define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
216: #define DRM_IOCTL_R128_CLEAR2     DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
217: #define DRM_IOCTL_R128_GETPARAM   DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
218: #define DRM_IOCTL_R128_FLIP       DRM_IO(  DRM_COMMAND_BASE + DRM_R128_FLIP)
219: 
220: typedef struct drm_r128_init {
221:         enum {
222:                 R128_INIT_CCE = 0x01,
223:                 R128_CLEANUP_CCE = 0x02
224:         } func;
225:         unsigned long sarea_priv_offset;
226:         int is_pci;
227:         int cce_mode;
228:         int cce_secure;
229:         int ring_size;
230:         int usec_timeout;
231: 
232:         unsigned int fb_bpp;
233:         unsigned int front_offset, front_pitch;
234:         unsigned int back_offset, back_pitch;
235:         unsigned int depth_bpp;
236:         unsigned int depth_offset, depth_pitch;
237:         unsigned int span_offset;
238: 
239:         unsigned long fb_offset;
240:         unsigned long mmio_offset;
241:         unsigned long ring_offset;
242:         unsigned long ring_rptr_offset;
243:         unsigned long buffers_offset;
244:         unsigned long agp_textures_offset;
245: } drm_r128_init_t;
246: 
247: typedef struct drm_r128_cce_stop {
248:         int flush;
249:         int idle;
250: } drm_r128_cce_stop_t;
251: 
252: typedef struct drm_r128_clear {
253:         unsigned int flags;
254:         unsigned int clear_color;
255:         unsigned int clear_depth;
256:         unsigned int color_mask;
257:         unsigned int depth_mask;
258: } drm_r128_clear_t;
259: 
260: typedef struct drm_r128_vertex {
261:         int prim;
262:         int idx;                /* Index of vertex buffer */
263:         int count;              /* Number of vertices in buffer */
264:         int discard;            /* Client finished with buffer? */
265: } drm_r128_vertex_t;
266: 
267: typedef struct drm_r128_indices {
268:         int prim;
269:         int idx;
270:         int start;
271:         int end;
272:         int discard;            /* Client finished with buffer? */
273: } drm_r128_indices_t;
274: 
275: typedef struct drm_r128_blit {
276:         int idx;
277:         int pitch;
278:         int offset;
279:         int format;
280:         unsigned short x, y;
281:         unsigned short width, height;
282: } drm_r128_blit_t;
283: 
284: typedef struct drm_r128_depth {
285:         enum {
286:                 R128_WRITE_SPAN = 0x01,
287:                 R128_WRITE_PIXELS = 0x02,
288:                 R128_READ_SPAN = 0x03,
289:                 R128_READ_PIXELS = 0x04
290:         } func;
291:         int n;
292:         int *x;
293:         int *y;
294:         unsigned int *buffer;
295:         unsigned char *mask;
296: } drm_r128_depth_t;
297: 
298: typedef struct drm_r128_stipple {
299:         unsigned int *mask;
300: } drm_r128_stipple_t;
301: 
302: typedef struct drm_r128_indirect {
303:         int idx;
304:         int start;
305:         int end;
306:         int discard;
307: } drm_r128_indirect_t;
308: 
309: typedef struct drm_r128_fullscreen {
310:         enum {
311:                 R128_INIT_FULLSCREEN = 0x01,
312:                 R128_CLEANUP_FULLSCREEN = 0x02
313:         } func;
314: } drm_r128_fullscreen_t;
315: 
316: /* 2.3: An ioctl to get parameters that aren't available to the 3d
317:  * client any other way.
318:  */
319: #define R128_PARAM_IRQ_NR            1
320: 
321: typedef struct drm_r128_getparam {
322:         int param;
323:         void *value;
324: } drm_r128_getparam_t;
325: 
326: #endif
327: 

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