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001: /*
002:  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
003:  * All Rights Reserved.
004:  *
005:  * Permission is hereby granted, free of charge, to any person obtaining a
006:  * copy of this software and associated documentation files (the
007:  * "Software"), to deal in the Software without restriction, including
008:  * without limitation the rights to use, copy, modify, merge, publish,
009:  * distribute, sub license, and/or sell copies of the Software, and to
010:  * permit persons to whom the Software is furnished to do so, subject to
011:  * the following conditions:
012:  *
013:  * The above copyright notice and this permission notice (including the
014:  * next paragraph) shall be included in all copies or substantial portions
015:  * of the Software.
016:  *
017:  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
018:  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
019:  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
020:  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
021:  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
022:  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
023:  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
024:  *
025:  */
026: 
027: #ifndef _I915_DRM_H_
028: #define _I915_DRM_H_
029: 
030: #include <drm/drm.h>
031: 
032: /* Please note that modifications to all structs defined here are
033:  * subject to backwards-compatibility constraints.
034:  */
035: 
036: 
037: /* Each region is a minimum of 16k, and there are at most 255 of them.
038:  */
039: #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
040:                                  * of chars for next/prev indices */
041: #define I915_LOG_MIN_TEX_REGION_SIZE 14
042: 
043: typedef struct _drm_i915_init {
044:         enum {
045:                 I915_INIT_DMA = 0x01,
046:                 I915_CLEANUP_DMA = 0x02,
047:                 I915_RESUME_DMA = 0x03
048:         } func;
049:         unsigned int mmio_offset;
050:         int sarea_priv_offset;
051:         unsigned int ring_start;
052:         unsigned int ring_end;
053:         unsigned int ring_size;
054:         unsigned int front_offset;
055:         unsigned int back_offset;
056:         unsigned int depth_offset;
057:         unsigned int w;
058:         unsigned int h;
059:         unsigned int pitch;
060:         unsigned int pitch_bits;
061:         unsigned int back_pitch;
062:         unsigned int depth_pitch;
063:         unsigned int cpp;
064:         unsigned int chipset;
065: } drm_i915_init_t;
066: 
067: typedef struct _drm_i915_sarea {
068:         struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
069:         int last_upload;        /* last time texture was uploaded */
070:         int last_enqueue;       /* last time a buffer was enqueued */
071:         int last_dispatch;      /* age of the most recently dispatched buffer */
072:         int ctxOwner;           /* last context to upload state */
073:         int texAge;
074:         int pf_enabled;         /* is pageflipping allowed? */
075:         int pf_active;
076:         int pf_current_page;    /* which buffer is being displayed? */
077:         int perf_boxes;         /* performance boxes to be displayed */
078:         int width, height;      /* screen size in pixels */
079: 
080:         drm_handle_t front_handle;
081:         int front_offset;
082:         int front_size;
083: 
084:         drm_handle_t back_handle;
085:         int back_offset;
086:         int back_size;
087: 
088:         drm_handle_t depth_handle;
089:         int depth_offset;
090:         int depth_size;
091: 
092:         drm_handle_t tex_handle;
093:         int tex_offset;
094:         int tex_size;
095:         int log_tex_granularity;
096:         int pitch;
097:         int rotation;           /* 0, 90, 180 or 270 */
098:         int rotated_offset;
099:         int rotated_size;
100:         int rotated_pitch;
101:         int virtualX, virtualY;
102: 
103:         unsigned int front_tiled;
104:         unsigned int back_tiled;
105:         unsigned int depth_tiled;
106:         unsigned int rotated_tiled;
107:         unsigned int rotated2_tiled;
108: 
109:         int pipeA_x;
110:         int pipeA_y;
111:         int pipeA_w;
112:         int pipeA_h;
113:         int pipeB_x;
114:         int pipeB_y;
115:         int pipeB_w;
116:         int pipeB_h;
117: 
118:         /* fill out some space for old userspace triple buffer */
119:         drm_handle_t unused_handle;
120:         __u32 unused1, unused2, unused3;
121: 
122:         /* buffer object handles for static buffers. May change
123:          * over the lifetime of the client.
124:          */
125:         __u32 front_bo_handle;
126:         __u32 back_bo_handle;
127:         __u32 unused_bo_handle;
128:         __u32 depth_bo_handle;
129: 
130: } drm_i915_sarea_t;
131: 
132: /* due to userspace building against these headers we need some compat here */
133: #define planeA_x pipeA_x
134: #define planeA_y pipeA_y
135: #define planeA_w pipeA_w
136: #define planeA_h pipeA_h
137: #define planeB_x pipeB_x
138: #define planeB_y pipeB_y
139: #define planeB_w pipeB_w
140: #define planeB_h pipeB_h
141: 
142: /* Flags for perf_boxes
143:  */
144: #define I915_BOX_RING_EMPTY    0x1
145: #define I915_BOX_FLIP          0x2
146: #define I915_BOX_WAIT          0x4
147: #define I915_BOX_TEXTURE_LOAD  0x8
148: #define I915_BOX_LOST_CONTEXT  0x10
149: 
150: /* I915 specific ioctls
151:  * The device specific ioctl range is 0x40 to 0x79.
152:  */
153: #define DRM_I915_INIT           0x00
154: #define DRM_I915_FLUSH          0x01
155: #define DRM_I915_FLIP           0x02
156: #define DRM_I915_BATCHBUFFER    0x03
157: #define DRM_I915_IRQ_EMIT       0x04
158: #define DRM_I915_IRQ_WAIT       0x05
159: #define DRM_I915_GETPARAM       0x06
160: #define DRM_I915_SETPARAM       0x07
161: #define DRM_I915_ALLOC          0x08
162: #define DRM_I915_FREE           0x09
163: #define DRM_I915_INIT_HEAP      0x0a
164: #define DRM_I915_CMDBUFFER      0x0b
165: #define DRM_I915_DESTROY_HEAP   0x0c
166: #define DRM_I915_SET_VBLANK_PIPE        0x0d
167: #define DRM_I915_GET_VBLANK_PIPE        0x0e
168: #define DRM_I915_VBLANK_SWAP    0x0f
169: #define DRM_I915_HWS_ADDR       0x11
170: #define DRM_I915_GEM_INIT       0x13
171: #define DRM_I915_GEM_EXECBUFFER 0x14
172: #define DRM_I915_GEM_PIN        0x15
173: #define DRM_I915_GEM_UNPIN      0x16
174: #define DRM_I915_GEM_BUSY       0x17
175: #define DRM_I915_GEM_THROTTLE   0x18
176: #define DRM_I915_GEM_ENTERVT    0x19
177: #define DRM_I915_GEM_LEAVEVT    0x1a
178: #define DRM_I915_GEM_CREATE     0x1b
179: #define DRM_I915_GEM_PREAD      0x1c
180: #define DRM_I915_GEM_PWRITE     0x1d
181: #define DRM_I915_GEM_MMAP       0x1e
182: #define DRM_I915_GEM_SET_DOMAIN 0x1f
183: #define DRM_I915_GEM_SW_FINISH  0x20
184: #define DRM_I915_GEM_SET_TILING 0x21
185: #define DRM_I915_GEM_GET_TILING 0x22
186: #define DRM_I915_GEM_GET_APERTURE 0x23
187: #define DRM_I915_GEM_MMAP_GTT   0x24
188: #define DRM_I915_GET_PIPE_FROM_CRTC_ID  0x25
189: #define DRM_I915_GEM_MADVISE    0x26
190: #define DRM_I915_OVERLAY_PUT_IMAGE      0x27
191: #define DRM_I915_OVERLAY_ATTRS  0x28
192: #define DRM_I915_GEM_EXECBUFFER2        0x29
193: 
194: #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
195: #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
196: #define DRM_IOCTL_I915_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
197: #define DRM_IOCTL_I915_BATCHBUFFER      DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
198: #define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
199: #define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
200: #define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
201: #define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
202: #define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
203: #define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
204: #define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
205: #define DRM_IOCTL_I915_CMDBUFFER        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
206: #define DRM_IOCTL_I915_DESTROY_HEAP     DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
207: #define DRM_IOCTL_I915_SET_VBLANK_PIPE  DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
208: #define DRM_IOCTL_I915_GET_VBLANK_PIPE  DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
209: #define DRM_IOCTL_I915_VBLANK_SWAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
210: #define DRM_IOCTL_I915_HWS_ADDR         DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
211: #define DRM_IOCTL_I915_GEM_INIT         DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
212: #define DRM_IOCTL_I915_GEM_EXECBUFFER   DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
213: #define DRM_IOCTL_I915_GEM_EXECBUFFER2  DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
214: #define DRM_IOCTL_I915_GEM_PIN          DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
215: #define DRM_IOCTL_I915_GEM_UNPIN        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
216: #define DRM_IOCTL_I915_GEM_BUSY         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
217: #define DRM_IOCTL_I915_GEM_THROTTLE     DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
218: #define DRM_IOCTL_I915_GEM_ENTERVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
219: #define DRM_IOCTL_I915_GEM_LEAVEVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
220: #define DRM_IOCTL_I915_GEM_CREATE       DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
221: #define DRM_IOCTL_I915_GEM_PREAD        DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
222: #define DRM_IOCTL_I915_GEM_PWRITE       DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
223: #define DRM_IOCTL_I915_GEM_MMAP         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
224: #define DRM_IOCTL_I915_GEM_MMAP_GTT     DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
225: #define DRM_IOCTL_I915_GEM_SET_DOMAIN   DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
226: #define DRM_IOCTL_I915_GEM_SW_FINISH    DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
227: #define DRM_IOCTL_I915_GEM_SET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
228: #define DRM_IOCTL_I915_GEM_GET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
229: #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
230: #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
231: #define DRM_IOCTL_I915_GEM_MADVISE      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
232: #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
233: #define DRM_IOCTL_I915_OVERLAY_ATTRS    DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
234: 
235: /* Allow drivers to submit batchbuffers directly to hardware, relying
236:  * on the security mechanisms provided by hardware.
237:  */
238: typedef struct drm_i915_batchbuffer {
239:         int start;              /* agp offset */
240:         int used;               /* nr bytes in use */
241:         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
242:         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
243:         int num_cliprects;      /* mulitpass with multiple cliprects? */
244:         struct drm_clip_rect *cliprects;        /* pointer to userspace cliprects */
245: } drm_i915_batchbuffer_t;
246: 
247: /* As above, but pass a pointer to userspace buffer which can be
248:  * validated by the kernel prior to sending to hardware.
249:  */
250: typedef struct _drm_i915_cmdbuffer {
251:         char *buf;      /* pointer to userspace command buffer */
252:         int sz;                 /* nr bytes in buf */
253:         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
254:         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
255:         int num_cliprects;      /* mulitpass with multiple cliprects? */
256:         struct drm_clip_rect *cliprects;        /* pointer to userspace cliprects */
257: } drm_i915_cmdbuffer_t;
258: 
259: /* Userspace can request & wait on irq's:
260:  */
261: typedef struct drm_i915_irq_emit {
262:         int *irq_seq;
263: } drm_i915_irq_emit_t;
264: 
265: typedef struct drm_i915_irq_wait {
266:         int irq_seq;
267: } drm_i915_irq_wait_t;
268: 
269: /* Ioctl to query kernel params:
270:  */
271: #define I915_PARAM_IRQ_ACTIVE            1
272: #define I915_PARAM_ALLOW_BATCHBUFFER     2
273: #define I915_PARAM_LAST_DISPATCH         3
274: #define I915_PARAM_CHIPSET_ID            4
275: #define I915_PARAM_HAS_GEM               5
276: #define I915_PARAM_NUM_FENCES_AVAIL      6
277: #define I915_PARAM_HAS_OVERLAY           7
278: #define I915_PARAM_HAS_PAGEFLIPPING      8
279: #define I915_PARAM_HAS_EXECBUF2          9
280: #define I915_PARAM_HAS_BSD               10
281: #define I915_PARAM_HAS_BLT               11
282: #define I915_PARAM_HAS_RELAXED_FENCING   12
283: #define I915_PARAM_HAS_COHERENT_RINGS    13
284: #define I915_PARAM_HAS_EXEC_CONSTANTS    14
285: #define I915_PARAM_HAS_RELAXED_DELTA     15
286: #define I915_PARAM_HAS_GEN7_SOL_RESET    16
287: 
288: typedef struct drm_i915_getparam {
289:         int param;
290:         int *value;
291: } drm_i915_getparam_t;
292: 
293: /* Ioctl to set kernel params:
294:  */
295: #define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
296: #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
297: #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
298: #define I915_SETPARAM_NUM_USED_FENCES                     4
299: 
300: typedef struct drm_i915_setparam {
301:         int param;
302:         int value;
303: } drm_i915_setparam_t;
304: 
305: /* A memory manager for regions of shared memory:
306:  */
307: #define I915_MEM_REGION_AGP 1
308: 
309: typedef struct drm_i915_mem_alloc {
310:         int region;
311:         int alignment;
312:         int size;
313:         int *region_offset;     /* offset from start of fb or agp */
314: } drm_i915_mem_alloc_t;
315: 
316: typedef struct drm_i915_mem_free {
317:         int region;
318:         int region_offset;
319: } drm_i915_mem_free_t;
320: 
321: typedef struct drm_i915_mem_init_heap {
322:         int region;
323:         int size;
324:         int start;
325: } drm_i915_mem_init_heap_t;
326: 
327: /* Allow memory manager to be torn down and re-initialized (eg on
328:  * rotate):
329:  */
330: typedef struct drm_i915_mem_destroy_heap {
331:         int region;
332: } drm_i915_mem_destroy_heap_t;
333: 
334: /* Allow X server to configure which pipes to monitor for vblank signals
335:  */
336: #define DRM_I915_VBLANK_PIPE_A  1
337: #define DRM_I915_VBLANK_PIPE_B  2
338: 
339: typedef struct drm_i915_vblank_pipe {
340:         int pipe;
341: } drm_i915_vblank_pipe_t;
342: 
343: /* Schedule buffer swap at given vertical blank:
344:  */
345: typedef struct drm_i915_vblank_swap {
346:         drm_drawable_t drawable;
347:         enum drm_vblank_seq_type seqtype;
348:         unsigned int sequence;
349: } drm_i915_vblank_swap_t;
350: 
351: typedef struct drm_i915_hws_addr {
352:         __u64 addr;
353: } drm_i915_hws_addr_t;
354: 
355: struct drm_i915_gem_init {
356:         /**
357:          * Beginning offset in the GTT to be managed by the DRM memory
358:          * manager.
359:          */
360:         __u64 gtt_start;
361:         /**
362:          * Ending offset in the GTT to be managed by the DRM memory
363:          * manager.
364:          */
365:         __u64 gtt_end;
366: };
367: 
368: struct drm_i915_gem_create {
369:         /**
370:          * Requested size for the object.
371:          *
372:          * The (page-aligned) allocated size for the object will be returned.
373:          */
374:         __u64 size;
375:         /**
376:          * Returned handle for the object.
377:          *
378:          * Object handles are nonzero.
379:          */
380:         __u32 handle;
381:         __u32 pad;
382: };
383: 
384: struct drm_i915_gem_pread {
385:         /** Handle for the object being read. */
386:         __u32 handle;
387:         __u32 pad;
388:         /** Offset into the object to read from */
389:         __u64 offset;
390:         /** Length of data to read */
391:         __u64 size;
392:         /**
393:          * Pointer to write the data into.
394:          *
395:          * This is a fixed-size type for 32/64 compatibility.
396:          */
397:         __u64 data_ptr;
398: };
399: 
400: struct drm_i915_gem_pwrite {
401:         /** Handle for the object being written to. */
402:         __u32 handle;
403:         __u32 pad;
404:         /** Offset into the object to write to */
405:         __u64 offset;
406:         /** Length of data to write */
407:         __u64 size;
408:         /**
409:          * Pointer to read the data from.
410:          *
411:          * This is a fixed-size type for 32/64 compatibility.
412:          */
413:         __u64 data_ptr;
414: };
415: 
416: struct drm_i915_gem_mmap {
417:         /** Handle for the object being mapped. */
418:         __u32 handle;
419:         __u32 pad;
420:         /** Offset in the object to map. */
421:         __u64 offset;
422:         /**
423:          * Length of data to map.
424:          *
425:          * The value will be page-aligned.
426:          */
427:         __u64 size;
428:         /**
429:          * Returned pointer the data was mapped at.
430:          *
431:          * This is a fixed-size type for 32/64 compatibility.
432:          */
433:         __u64 addr_ptr;
434: };
435: 
436: struct drm_i915_gem_mmap_gtt {
437:         /** Handle for the object being mapped. */
438:         __u32 handle;
439:         __u32 pad;
440:         /**
441:          * Fake offset to use for subsequent mmap call
442:          *
443:          * This is a fixed-size type for 32/64 compatibility.
444:          */
445:         __u64 offset;
446: };
447: 
448: struct drm_i915_gem_set_domain {
449:         /** Handle for the object */
450:         __u32 handle;
451: 
452:         /** New read domains */
453:         __u32 read_domains;
454: 
455:         /** New write domain */
456:         __u32 write_domain;
457: };
458: 
459: struct drm_i915_gem_sw_finish {
460:         /** Handle for the object */
461:         __u32 handle;
462: };
463: 
464: struct drm_i915_gem_relocation_entry {
465:         /**
466:          * Handle of the buffer being pointed to by this relocation entry.
467:          *
468:          * It's appealing to make this be an index into the mm_validate_entry
469:          * list to refer to the buffer, but this allows the driver to create
470:          * a relocation list for state buffers and not re-write it per
471:          * exec using the buffer.
472:          */
473:         __u32 target_handle;
474: 
475:         /**
476:          * Value to be added to the offset of the target buffer to make up
477:          * the relocation entry.
478:          */
479:         __u32 delta;
480: 
481:         /** Offset in the buffer the relocation entry will be written into */
482:         __u64 offset;
483: 
484:         /**
485:          * Offset value of the target buffer that the relocation entry was last
486:          * written as.
487:          *
488:          * If the buffer has the same offset as last time, we can skip syncing
489:          * and writing the relocation.  This value is written back out by
490:          * the execbuffer ioctl when the relocation is written.
491:          */
492:         __u64 presumed_offset;
493: 
494:         /**
495:          * Target memory domains read by this operation.
496:          */
497:         __u32 read_domains;
498: 
499:         /**
500:          * Target memory domains written by this operation.
501:          *
502:          * Note that only one domain may be written by the whole
503:          * execbuffer operation, so that where there are conflicts,
504:          * the application will get -EINVAL back.
505:          */
506:         __u32 write_domain;
507: };
508: 
509: /** @{
510:  * Intel memory domains
511:  *
512:  * Most of these just align with the various caches in
513:  * the system and are used to flush and invalidate as
514:  * objects end up cached in different domains.
515:  */
516: /** CPU cache */
517: #define I915_GEM_DOMAIN_CPU             0x00000001
518: /** Render cache, used by 2D and 3D drawing */
519: #define I915_GEM_DOMAIN_RENDER          0x00000002
520: /** Sampler cache, used by texture engine */
521: #define I915_GEM_DOMAIN_SAMPLER         0x00000004
522: /** Command queue, used to load batch buffers */
523: #define I915_GEM_DOMAIN_COMMAND         0x00000008
524: /** Instruction cache, used by shader programs */
525: #define I915_GEM_DOMAIN_INSTRUCTION     0x00000010
526: /** Vertex address cache */
527: #define I915_GEM_DOMAIN_VERTEX          0x00000020
528: /** GTT domain - aperture and scanout */
529: #define I915_GEM_DOMAIN_GTT             0x00000040
530: /** @} */
531: 
532: struct drm_i915_gem_exec_object {
533:         /**
534:          * User's handle for a buffer to be bound into the GTT for this
535:          * operation.
536:          */
537:         __u32 handle;
538: 
539:         /** Number of relocations to be performed on this buffer */
540:         __u32 relocation_count;
541:         /**
542:          * Pointer to array of struct drm_i915_gem_relocation_entry containing
543:          * the relocations to be performed in this buffer.
544:          */
545:         __u64 relocs_ptr;
546: 
547:         /** Required alignment in graphics aperture */
548:         __u64 alignment;
549: 
550:         /**
551:          * Returned value of the updated offset of the object, for future
552:          * presumed_offset writes.
553:          */
554:         __u64 offset;
555: };
556: 
557: struct drm_i915_gem_execbuffer {
558:         /**
559:          * List of buffers to be validated with their relocations to be
560:          * performend on them.
561:          *
562:          * This is a pointer to an array of struct drm_i915_gem_validate_entry.
563:          *
564:          * These buffers must be listed in an order such that all relocations
565:          * a buffer is performing refer to buffers that have already appeared
566:          * in the validate list.
567:          */
568:         __u64 buffers_ptr;
569:         __u32 buffer_count;
570: 
571:         /** Offset in the batchbuffer to start execution from. */
572:         __u32 batch_start_offset;
573:         /** Bytes used in batchbuffer from batch_start_offset */
574:         __u32 batch_len;
575:         __u32 DR1;
576:         __u32 DR4;
577:         __u32 num_cliprects;
578:         /** This is a struct drm_clip_rect *cliprects */
579:         __u64 cliprects_ptr;
580: };
581: 
582: struct drm_i915_gem_exec_object2 {
583:         /**
584:          * User's handle for a buffer to be bound into the GTT for this
585:          * operation.
586:          */
587:         __u32 handle;
588: 
589:         /** Number of relocations to be performed on this buffer */
590:         __u32 relocation_count;
591:         /**
592:          * Pointer to array of struct drm_i915_gem_relocation_entry containing
593:          * the relocations to be performed in this buffer.
594:          */
595:         __u64 relocs_ptr;
596: 
597:         /** Required alignment in graphics aperture */
598:         __u64 alignment;
599: 
600:         /**
601:          * Returned value of the updated offset of the object, for future
602:          * presumed_offset writes.
603:          */
604:         __u64 offset;
605: 
606: #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
607:         __u64 flags;
608:         __u64 rsvd1;
609:         __u64 rsvd2;
610: };
611: 
612: struct drm_i915_gem_execbuffer2 {
613:         /**
614:          * List of gem_exec_object2 structs
615:          */
616:         __u64 buffers_ptr;
617:         __u32 buffer_count;
618: 
619:         /** Offset in the batchbuffer to start execution from. */
620:         __u32 batch_start_offset;
621:         /** Bytes used in batchbuffer from batch_start_offset */
622:         __u32 batch_len;
623:         __u32 DR1;
624:         __u32 DR4;
625:         __u32 num_cliprects;
626:         /** This is a struct drm_clip_rect *cliprects */
627:         __u64 cliprects_ptr;
628: #define I915_EXEC_RING_MASK              (7<<0)
629: #define I915_EXEC_DEFAULT                (0<<0)
630: #define I915_EXEC_RENDER                 (1<<0)
631: #define I915_EXEC_BSD                    (2<<0)
632: #define I915_EXEC_BLT                    (3<<0)
633: 
634: /* Used for switching the constants addressing mode on gen4+ RENDER ring.
635:  * Gen6+ only supports relative addressing to dynamic state (default) and
636:  * absolute addressing.
637:  *
638:  * These flags are ignored for the BSD and BLT rings.
639:  */
640: #define I915_EXEC_CONSTANTS_MASK        (3<<6)
641: #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
642: #define I915_EXEC_CONSTANTS_ABSOLUTE    (1<<6)
643: #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
644:         __u64 flags;
645:         __u64 rsvd1;
646:         __u64 rsvd2;
647: };
648: 
649: /** Resets the SO write offset registers for transform feedback on gen7. */
650: #define I915_EXEC_GEN7_SOL_RESET        (1<<8)
651: 
652: struct drm_i915_gem_pin {
653:         /** Handle of the buffer to be pinned. */
654:         __u32 handle;
655:         __u32 pad;
656: 
657:         /** alignment required within the aperture */
658:         __u64 alignment;
659: 
660:         /** Returned GTT offset of the buffer. */
661:         __u64 offset;
662: };
663: 
664: struct drm_i915_gem_unpin {
665:         /** Handle of the buffer to be unpinned. */
666:         __u32 handle;
667:         __u32 pad;
668: };
669: 
670: struct drm_i915_gem_busy {
671:         /** Handle of the buffer to check for busy */
672:         __u32 handle;
673: 
674:         /** Return busy status (1 if busy, 0 if idle) */
675:         __u32 busy;
676: };
677: 
678: #define I915_TILING_NONE        0
679: #define I915_TILING_X           1
680: #define I915_TILING_Y           2
681: 
682: #define I915_BIT_6_SWIZZLE_NONE         0
683: #define I915_BIT_6_SWIZZLE_9            1
684: #define I915_BIT_6_SWIZZLE_9_10         2
685: #define I915_BIT_6_SWIZZLE_9_11         3
686: #define I915_BIT_6_SWIZZLE_9_10_11      4
687: /* Not seen by userland */
688: #define I915_BIT_6_SWIZZLE_UNKNOWN      5
689: /* Seen by userland. */
690: #define I915_BIT_6_SWIZZLE_9_17         6
691: #define I915_BIT_6_SWIZZLE_9_10_17      7
692: 
693: struct drm_i915_gem_set_tiling {
694:         /** Handle of the buffer to have its tiling state updated */
695:         __u32 handle;
696: 
697:         /**
698:          * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
699:          * I915_TILING_Y).
700:          *
701:          * This value is to be set on request, and will be updated by the
702:          * kernel on successful return with the actual chosen tiling layout.
703:          *
704:          * The tiling mode may be demoted to I915_TILING_NONE when the system
705:          * has bit 6 swizzling that can't be managed correctly by GEM.
706:          *
707:          * Buffer contents become undefined when changing tiling_mode.
708:          */
709:         __u32 tiling_mode;
710: 
711:         /**
712:          * Stride in bytes for the object when in I915_TILING_X or
713:          * I915_TILING_Y.
714:          */
715:         __u32 stride;
716: 
717:         /**
718:          * Returned address bit 6 swizzling required for CPU access through
719:          * mmap mapping.
720:          */
721:         __u32 swizzle_mode;
722: };
723: 
724: struct drm_i915_gem_get_tiling {
725:         /** Handle of the buffer to get tiling state for. */
726:         __u32 handle;
727: 
728:         /**
729:          * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
730:          * I915_TILING_Y).
731:          */
732:         __u32 tiling_mode;
733: 
734:         /**
735:          * Returned address bit 6 swizzling required for CPU access through
736:          * mmap mapping.
737:          */
738:         __u32 swizzle_mode;
739: };
740: 
741: struct drm_i915_gem_get_aperture {
742:         /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
743:         __u64 aper_size;
744: 
745:         /**
746:          * Available space in the aperture used by i915_gem_execbuffer, in
747:          * bytes
748:          */
749:         __u64 aper_available_size;
750: };
751: 
752: struct drm_i915_get_pipe_from_crtc_id {
753:         /** ID of CRTC being requested **/
754:         __u32 crtc_id;
755: 
756:         /** pipe of requested CRTC **/
757:         __u32 pipe;
758: };
759: 
760: #define I915_MADV_WILLNEED 0
761: #define I915_MADV_DONTNEED 1
762: #define __I915_MADV_PURGED 2 /* internal state */
763: 
764: struct drm_i915_gem_madvise {
765:         /** Handle of the buffer to change the backing store advice */
766:         __u32 handle;
767: 
768:         /* Advice: either the buffer will be needed again in the near future,
769:          *         or wont be and could be discarded under memory pressure.
770:          */
771:         __u32 madv;
772: 
773:         /** Whether the backing store still exists. */
774:         __u32 retained;
775: };
776: 
777: /* flags */
778: #define I915_OVERLAY_TYPE_MASK          0xff
779: #define I915_OVERLAY_YUV_PLANAR         0x01
780: #define I915_OVERLAY_YUV_PACKED         0x02
781: #define I915_OVERLAY_RGB                0x03
782: 
783: #define I915_OVERLAY_DEPTH_MASK         0xff00
784: #define I915_OVERLAY_RGB24              0x1000
785: #define I915_OVERLAY_RGB16              0x2000
786: #define I915_OVERLAY_RGB15              0x3000
787: #define I915_OVERLAY_YUV422             0x0100
788: #define I915_OVERLAY_YUV411             0x0200
789: #define I915_OVERLAY_YUV420             0x0300
790: #define I915_OVERLAY_YUV410             0x0400
791: 
792: #define I915_OVERLAY_SWAP_MASK          0xff0000
793: #define I915_OVERLAY_NO_SWAP            0x000000
794: #define I915_OVERLAY_UV_SWAP            0x010000
795: #define I915_OVERLAY_Y_SWAP             0x020000
796: #define I915_OVERLAY_Y_AND_UV_SWAP      0x030000
797: 
798: #define I915_OVERLAY_FLAGS_MASK         0xff000000
799: #define I915_OVERLAY_ENABLE             0x01000000
800: 
801: struct drm_intel_overlay_put_image {
802:         /* various flags and src format description */
803:         __u32 flags;
804:         /* source picture description */
805:         __u32 bo_handle;
806:         /* stride values and offsets are in bytes, buffer relative */
807:         __u16 stride_Y; /* stride for packed formats */
808:         __u16 stride_UV;
809:         __u32 offset_Y; /* offset for packet formats */
810:         __u32 offset_U;
811:         __u32 offset_V;
812:         /* in pixels */
813:         __u16 src_width;
814:         __u16 src_height;
815:         /* to compensate the scaling factors for partially covered surfaces */
816:         __u16 src_scan_width;
817:         __u16 src_scan_height;
818:         /* output crtc description */
819:         __u32 crtc_id;
820:         __u16 dst_x;
821:         __u16 dst_y;
822:         __u16 dst_width;
823:         __u16 dst_height;
824: };
825: 
826: /* flags */
827: #define I915_OVERLAY_UPDATE_ATTRS       (1<<0)
828: #define I915_OVERLAY_UPDATE_GAMMA       (1<<1)
829: struct drm_intel_overlay_attrs {
830:         __u32 flags;
831:         __u32 color_key;
832:         __s32 brightness;
833:         __u32 contrast;
834:         __u32 saturation;
835:         __u32 gamma0;
836:         __u32 gamma1;
837:         __u32 gamma2;
838:         __u32 gamma3;
839:         __u32 gamma4;
840:         __u32 gamma5;
841: };
842: 
843: #endif                          /* _I915_DRM_H_ */
844: 

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