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001: #ifndef _I810_DRM_H_
002: #define _I810_DRM_H_
003: 
004: /* WARNING: These defines must be the same as what the Xserver uses.
005:  * if you change them, you must change the defines in the Xserver.
006:  */
007: 
008: #ifndef _I810_DEFINES_
009: #define _I810_DEFINES_
010: 
011: #define I810_DMA_BUF_ORDER              12
012: #define I810_DMA_BUF_SZ                 (1<<I810_DMA_BUF_ORDER)
013: #define I810_DMA_BUF_NR                 256
014: #define I810_NR_SAREA_CLIPRECTS         8
015: 
016: /* Each region is a minimum of 64k, and there are at most 64 of them.
017:  */
018: #define I810_NR_TEX_REGIONS 64
019: #define I810_LOG_MIN_TEX_REGION_SIZE 16
020: #endif
021: 
022: #define I810_UPLOAD_TEX0IMAGE  0x1      /* handled clientside */
023: #define I810_UPLOAD_TEX1IMAGE  0x2      /* handled clientside */
024: #define I810_UPLOAD_CTX        0x4
025: #define I810_UPLOAD_BUFFERS    0x8
026: #define I810_UPLOAD_TEX0       0x10
027: #define I810_UPLOAD_TEX1       0x20
028: #define I810_UPLOAD_CLIPRECTS  0x40
029: 
030: /* Indices into buf.Setup where various bits of state are mirrored per
031:  * context and per buffer.  These can be fired at the card as a unit,
032:  * or in a piecewise fashion as required.
033:  */
034: 
035: /* Destbuffer state
036:  *    - backbuffer linear offset and pitch -- invarient in the current dri
037:  *    - zbuffer linear offset and pitch -- also invarient
038:  *    - drawing origin in back and depth buffers.
039:  *
040:  * Keep the depth/back buffer state here to accommodate private buffers
041:  * in the future.
042:  */
043: #define I810_DESTREG_DI0  0     /* CMD_OP_DESTBUFFER_INFO (2 dwords) */
044: #define I810_DESTREG_DI1  1
045: #define I810_DESTREG_DV0  2     /* GFX_OP_DESTBUFFER_VARS (2 dwords) */
046: #define I810_DESTREG_DV1  3
047: #define I810_DESTREG_DR0  4     /* GFX_OP_DRAWRECT_INFO (4 dwords) */
048: #define I810_DESTREG_DR1  5
049: #define I810_DESTREG_DR2  6
050: #define I810_DESTREG_DR3  7
051: #define I810_DESTREG_DR4  8
052: #define I810_DEST_SETUP_SIZE 10
053: 
054: /* Context state
055:  */
056: #define I810_CTXREG_CF0   0     /* GFX_OP_COLOR_FACTOR */
057: #define I810_CTXREG_CF1   1
058: #define I810_CTXREG_ST0   2     /* GFX_OP_STIPPLE */
059: #define I810_CTXREG_ST1   3
060: #define I810_CTXREG_VF    4     /* GFX_OP_VERTEX_FMT */
061: #define I810_CTXREG_MT    5     /* GFX_OP_MAP_TEXELS */
062: #define I810_CTXREG_MC0   6     /* GFX_OP_MAP_COLOR_STAGES - stage 0 */
063: #define I810_CTXREG_MC1   7     /* GFX_OP_MAP_COLOR_STAGES - stage 1 */
064: #define I810_CTXREG_MC2   8     /* GFX_OP_MAP_COLOR_STAGES - stage 2 */
065: #define I810_CTXREG_MA0   9     /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
066: #define I810_CTXREG_MA1   10    /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
067: #define I810_CTXREG_MA2   11    /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */
068: #define I810_CTXREG_SDM   12    /* GFX_OP_SRC_DEST_MONO */
069: #define I810_CTXREG_FOG   13    /* GFX_OP_FOG_COLOR */
070: #define I810_CTXREG_B1    14    /* GFX_OP_BOOL_1 */
071: #define I810_CTXREG_B2    15    /* GFX_OP_BOOL_2 */
072: #define I810_CTXREG_LCS   16    /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */
073: #define I810_CTXREG_PV    17    /* GFX_OP_PV_RULE -- Invarient! */
074: #define I810_CTXREG_ZA    18    /* GFX_OP_ZBIAS_ALPHAFUNC */
075: #define I810_CTXREG_AA    19    /* GFX_OP_ANTIALIAS */
076: #define I810_CTX_SETUP_SIZE 20
077: 
078: /* Texture state (per tex unit)
079:  */
080: #define I810_TEXREG_MI0  0      /* GFX_OP_MAP_INFO (4 dwords) */
081: #define I810_TEXREG_MI1  1
082: #define I810_TEXREG_MI2  2
083: #define I810_TEXREG_MI3  3
084: #define I810_TEXREG_MF   4      /* GFX_OP_MAP_FILTER */
085: #define I810_TEXREG_MLC  5      /* GFX_OP_MAP_LOD_CTL */
086: #define I810_TEXREG_MLL  6      /* GFX_OP_MAP_LOD_LIMITS */
087: #define I810_TEXREG_MCS  7      /* GFX_OP_MAP_COORD_SETS ??? */
088: #define I810_TEX_SETUP_SIZE 8
089: 
090: /* Flags for clear ioctl
091:  */
092: #define I810_FRONT   0x1
093: #define I810_BACK    0x2
094: #define I810_DEPTH   0x4
095: 
096: typedef enum _drm_i810_init_func {
097:         I810_INIT_DMA = 0x01,
098:         I810_CLEANUP_DMA = 0x02,
099:         I810_INIT_DMA_1_4 = 0x03
100: } drm_i810_init_func_t;
101: 
102: /* This is the init structure after v1.2 */
103: typedef struct _drm_i810_init {
104:         drm_i810_init_func_t func;
105:         unsigned int mmio_offset;
106:         unsigned int buffers_offset;
107:         int sarea_priv_offset;
108:         unsigned int ring_start;
109:         unsigned int ring_end;
110:         unsigned int ring_size;
111:         unsigned int front_offset;
112:         unsigned int back_offset;
113:         unsigned int depth_offset;
114:         unsigned int overlay_offset;
115:         unsigned int overlay_physical;
116:         unsigned int w;
117:         unsigned int h;
118:         unsigned int pitch;
119:         unsigned int pitch_bits;
120: } drm_i810_init_t;
121: 
122: /* This is the init structure prior to v1.2 */
123: typedef struct _drm_i810_pre12_init {
124:         drm_i810_init_func_t func;
125:         unsigned int mmio_offset;
126:         unsigned int buffers_offset;
127:         int sarea_priv_offset;
128:         unsigned int ring_start;
129:         unsigned int ring_end;
130:         unsigned int ring_size;
131:         unsigned int front_offset;
132:         unsigned int back_offset;
133:         unsigned int depth_offset;
134:         unsigned int w;
135:         unsigned int h;
136:         unsigned int pitch;
137:         unsigned int pitch_bits;
138: } drm_i810_pre12_init_t;
139: 
140: /* Warning: If you change the SAREA structure you must change the Xserver
141:  * structure as well */
142: 
143: typedef struct _drm_i810_tex_region {
144:         unsigned char next, prev;       /* indices to form a circular LRU  */
145:         unsigned char in_use;   /* owned by a client, or free? */
146:         int age;                /* tracked by clients to update local LRU's */
147: } drm_i810_tex_region_t;
148: 
149: typedef struct _drm_i810_sarea {
150:         unsigned int ContextState[I810_CTX_SETUP_SIZE];
151:         unsigned int BufferState[I810_DEST_SETUP_SIZE];
152:         unsigned int TexState[2][I810_TEX_SETUP_SIZE];
153:         unsigned int dirty;
154: 
155:         unsigned int nbox;
156:         struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
157: 
158:         /* Maintain an LRU of contiguous regions of texture space.  If
159:          * you think you own a region of texture memory, and it has an
160:          * age different to the one you set, then you are mistaken and
161:          * it has been stolen by another client.  If global texAge
162:          * hasn't changed, there is no need to walk the list.
163:          *
164:          * These regions can be used as a proxy for the fine-grained
165:          * texture information of other clients - by maintaining them
166:          * in the same lru which is used to age their own textures,
167:          * clients have an approximate lru for the whole of global
168:          * texture space, and can make informed decisions as to which
169:          * areas to kick out.  There is no need to choose whether to
170:          * kick out your own texture or someone else's - simply eject
171:          * them all in LRU order.
172:          */
173: 
174:         drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
175:         /* Last elt is sentinal */
176:         int texAge;             /* last time texture was uploaded */
177:         int last_enqueue;       /* last time a buffer was enqueued */
178:         int last_dispatch;      /* age of the most recently dispatched buffer */
179:         int last_quiescent;     /*  */
180:         int ctxOwner;           /* last context to upload state */
181: 
182:         int vertex_prim;
183: 
184:         int pf_enabled;         /* is pageflipping allowed? */
185:         int pf_active;
186:         int pf_current_page;    /* which buffer is being displayed? */
187: } drm_i810_sarea_t;
188: 
189: /* WARNING: If you change any of these defines, make sure to change the
190:  * defines in the Xserver file (xf86drmMga.h)
191:  */
192: 
193: /* i810 specific ioctls
194:  * The device specific ioctl range is 0x40 to 0x79.
195:  */
196: #define DRM_I810_INIT           0x00
197: #define DRM_I810_VERTEX         0x01
198: #define DRM_I810_CLEAR          0x02
199: #define DRM_I810_FLUSH          0x03
200: #define DRM_I810_GETAGE         0x04
201: #define DRM_I810_GETBUF         0x05
202: #define DRM_I810_SWAP           0x06
203: #define DRM_I810_COPY           0x07
204: #define DRM_I810_DOCOPY         0x08
205: #define DRM_I810_OV0INFO        0x09
206: #define DRM_I810_FSTATUS        0x0a
207: #define DRM_I810_OV0FLIP        0x0b
208: #define DRM_I810_MC             0x0c
209: #define DRM_I810_RSTATUS        0x0d
210: #define DRM_I810_FLIP           0x0e
211: 
212: #define DRM_IOCTL_I810_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
213: #define DRM_IOCTL_I810_VERTEX           DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
214: #define DRM_IOCTL_I810_CLEAR            DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
215: #define DRM_IOCTL_I810_FLUSH            DRM_IO(  DRM_COMMAND_BASE + DRM_I810_FLUSH)
216: #define DRM_IOCTL_I810_GETAGE           DRM_IO(  DRM_COMMAND_BASE + DRM_I810_GETAGE)
217: #define DRM_IOCTL_I810_GETBUF           DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
218: #define DRM_IOCTL_I810_SWAP             DRM_IO(  DRM_COMMAND_BASE + DRM_I810_SWAP)
219: #define DRM_IOCTL_I810_COPY             DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
220: #define DRM_IOCTL_I810_DOCOPY           DRM_IO(  DRM_COMMAND_BASE + DRM_I810_DOCOPY)
221: #define DRM_IOCTL_I810_OV0INFO          DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
222: #define DRM_IOCTL_I810_FSTATUS          DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS)
223: #define DRM_IOCTL_I810_OV0FLIP          DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
224: #define DRM_IOCTL_I810_MC               DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
225: #define DRM_IOCTL_I810_RSTATUS          DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS)
226: #define DRM_IOCTL_I810_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP)
227: 
228: typedef struct _drm_i810_clear {
229:         int clear_color;
230:         int clear_depth;
231:         int flags;
232: } drm_i810_clear_t;
233: 
234: /* These may be placeholders if we have more cliprects than
235:  * I810_NR_SAREA_CLIPRECTS.  In that case, the client sets discard to
236:  * false, indicating that the buffer will be dispatched again with a
237:  * new set of cliprects.
238:  */
239: typedef struct _drm_i810_vertex {
240:         int idx;                /* buffer index */
241:         int used;               /* nr bytes in use */
242:         int discard;            /* client is finished with the buffer? */
243: } drm_i810_vertex_t;
244: 
245: typedef struct _drm_i810_copy_t {
246:         int idx;                /* buffer index */
247:         int used;               /* nr bytes in use */
248:         void *address;          /* Address to copy from */
249: } drm_i810_copy_t;
250: 
251: #define PR_TRIANGLES         (0x0<<18)
252: #define PR_TRISTRIP_0        (0x1<<18)
253: #define PR_TRISTRIP_1        (0x2<<18)
254: #define PR_TRIFAN            (0x3<<18)
255: #define PR_POLYGON           (0x4<<18)
256: #define PR_LINES             (0x5<<18)
257: #define PR_LINESTRIP         (0x6<<18)
258: #define PR_RECTS             (0x7<<18)
259: #define PR_MASK              (0x7<<18)
260: 
261: typedef struct drm_i810_dma {
262:         void *virtual;
263:         int request_idx;
264:         int request_size;
265:         int granted;
266: } drm_i810_dma_t;
267: 
268: typedef struct _drm_i810_overlay_t {
269:         unsigned int offset;    /* Address of the Overlay Regs */
270:         unsigned int physical;
271: } drm_i810_overlay_t;
272: 
273: typedef struct _drm_i810_mc {
274:         int idx;                /* buffer index */
275:         int used;               /* nr bytes in use */
276:         int num_blocks;         /* number of GFXBlocks */
277:         int *length;            /* List of lengths for GFXBlocks (FUTURE) */
278:         unsigned int last_render;       /* Last Render Request */
279: } drm_i810_mc_t;
280: 
281: #endif                          /* _I810_DRM_H_ */
282: 

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